Features

Quad SPI supports the following features:

• Master only operation with SPI data-rate
  • Programmable SPI clock—HCLK/2, HCLK/4, or HCLK/6
  • Maximum data-rate is HCLK/2
• FIFOs
  • Transmit and Receive FIFO
  • 16-byte transmit FIFO depth
  • 32-byte receive FIFO depth
  • AHB interface transfers up to four bytes at a time
• SPI Protocol
  • Master operation
  • Motorola SPI supported
  • Slave Select operation in idle cycles configurable
  • Extended SPI operation (1, 2, and 4-bit)
  • QSPI operation (4-bit operation)
  • BSPI operation (2-bit operation)
  • Execute in place (XIP)
  • Three or four-byte SPI address.
• Frame Size
  • 8-bit frames directly
  • Back-to-back frame operation supports greater than 8-bit frames
  • Up to 4 GB Transfer (2 × 32 bytes)
• Processor overhead reduction
  • SPI Flash command/data packets with automatic data generation and discard function
• Direct Mode
  • Allows a CPU to directly control the SPI interface pins.