Contents

Introduction Features 1. Description 2. Configuration Summary 3. Ordering Information 4. Block Diagram 5. Pin Configurations 5.1. Pin Descriptions 5.1.1. VCC 5.1.2. GND 5.1.3. Port B (PB[7:0]) XTAL1/XTAL2/TOSC1/TOSC2 5.1.4. Port C (PC[5:0]) 5.1.5. PC6/RESET 5.1.6. Port D (PD[7:0]) 5.1.7. Port E (PE[3:0]) 5.1.8. AVCC 5.1.9. AREF 5.1.10. ADC[7:6] 6. I/O Multiplexing 7. Resources 8. About Code Examples 9. AVR CPU Core 9.1. Overview 9.2. ALU – Arithmetic Logic Unit 9.3. Status Register 9.3.1. Status Register 9.4. General Purpose Register File 9.4.1. The X-register, Y-register, and Z-register 9.5. Stack Pointer 9.5.1. Stack Pointer Register Low and High byte 9.6. Instruction Execution Timing 9.7. Reset and Interrupt Handling 9.7.1. Interrupt Response Time 10. AVR Memories 10.1. Overview 10.2. In-System Reprogrammable Flash Program Memory 10.3. SRAM Data Memory 10.3.1. Data Memory Access Times 10.4. EEPROM Data Memory 10.4.1. EEPROM Read/Write Access 10.4.2. Preventing EEPROM Corruption 10.5. I/O Memory 10.5.1. General Purpose I/O Registers 10.6. Register Description 10.6.1. Accessing 16-Bit Registers 10.6.2. EEPROM Address Register Low and High Byte 10.6.3. EEPROM Data Register 10.6.4. EEPROM Control Register 10.6.5. GPIOR2 – General Purpose I/O Register 2 10.6.6. GPIOR1 – General Purpose I/O Register 1 10.6.7. GPIOR0 – General Purpose I/O Register 0 11. System Clock and Clock Options 11.1. Clock Systems and Their Distribution 11.1.1. CPU Clock – clkCPU 11.1.2. I/O Clock – clkI/O 11.1.3. PTC Clock - clkPTC 11.1.4. Flash Clock – clkFLASH 11.1.5. Asynchronous Timer Clock – clkASY 11.1.6. ADC Clock – clkADC 11.2. Clock Sources 11.2.1. Default Clock Source 11.2.2. Clock Start-Up Sequence 11.2.3. Clock Source Connections 11.3. Low-Power Crystal Oscillator 11.4. Low Frequency Crystal Oscillator 11.5. Calibrated Internal RC Oscillator 11.6. 128 kHz Internal Oscillator 11.7. External Clock 11.8. Clock Output Buffer 11.9. Timer/Counter Oscillator 11.10. System Clock Prescaler 11.11. Register Description 11.11.1. Oscillator Calibration Register 11.11.2. Clock Prescaler Register 12. CFD - Clock Failure Detection mechanism 12.1. Overview 12.2. Features 12.3. Operations 12.4. Timing Diagram 12.5. Register Description 12.5.1. XOSC Failure Detection Control And Status Register 13. Power Management and Sleep Modes 13.1. Overview 13.2. Sleep Modes 13.3. BOD Disable 13.4. Idle Mode 13.5. ADC Noise Reduction Mode 13.6. Power-Down Mode 13.7. Power-Save Mode 13.8. Standby Mode 13.9. Extended Standby Mode 13.10. Power Reduction Registers 13.11. Minimizing Power Consumption 13.11.1. Analog-to-Digital Converter 13.11.2. Analog Comparator 13.11.3. Brown-Out Detector 13.11.4. Internal Voltage Reference 13.11.5. Watchdog Timer 13.11.6. Port Pins 13.11.7. On-chip Debug System 13.12. Register Description 13.12.1. Sleep Mode Control Register 13.12.2. MCU Control Register 13.12.3. Power Reduction Register 0 13.12.4. Power Reduction Register 1 14. System Control and Reset 14.1. Resetting the AVR 14.2. Reset Sources 14.3. Power-on Reset 14.4. External Reset 14.5. Brown-out Detection 14.6. Watchdog System Reset 14.7. Internal Voltage Reference 14.7.1. Voltage Reference Enable Signals and Start-up Time 14.8. Watchdog Timer 14.8.1. Features 14.8.2. Overview 14.9. Register Description 14.9.1. MCU Status Register 14.9.2. WDTCSR – Watchdog Timer Control Register 15. INT - Interrupts 15.1. Interrupt Vectors in ATmega328PB 15.2. Register Description 15.2.1. Moving Interrupts Between Application and Boot Space 15.2.2. MCU Control Register 16. EXTINT - External Interrupts 16.1. Pin Change Interrupt Timing 16.2. Register Description 16.2.1. External Interrupt Control Register A 16.2.2. External Interrupt Mask Register 16.2.3. External Interrupt Flag Register 16.2.4. Pin Change Interrupt Control Register 16.2.5. Pin Change Interrupt Flag Register 16.2.6. Pin Change Mask Register 3 16.2.7. Pin Change Mask Register 2 16.2.8. Pin Change Mask Register 1 16.2.9. Pin Change Mask Register 0 17. I/O-Ports 17.1. Overview 17.2. Ports as General Digital I/O 17.2.1. Configuring the Pin 17.2.2. Toggling the Pin 17.2.3. Switching Between Input and Output 17.2.4. Reading the Pin Value 17.2.5. Digital Input Enable and Sleep Modes 17.2.6. Unconnected Pins 17.3. Alternate Port Functions 17.3.1. Alternate Functions of Port B 17.3.2. Alternate Functions of Port C 17.3.3. Alternate Functions of Port D 17.3.4. Alternate Functions of Port E 17.4. Register Description 17.4.1. MCU Control Register 17.4.2. Port B Data Register 17.4.3. Port B Data Direction Register 17.4.4. Port B Input Pins Address 17.4.5. Port C Data Register 17.4.6. Port C Data Direction Register 17.4.7. Port C Input Pins Address 17.4.8. Port D Data Register 17.4.9. Port D Data Direction Register 17.4.10. Port D Input Pins Address 17.4.11. Port E Data Register 17.4.12. Port E Data Direction Register 17.4.13. Port E Input Pins Address 18. TC0 - 8-bit Timer/Counter0 with PWM 18.1. Features 18.2. Overview 18.2.1. Definitions 18.2.2. Registers 18.3. Timer/Counter Clock Sources 18.4. Counter Unit 18.5. Output Compare Unit 18.5.1. Force Output Compare 18.5.2. Compare Match Blocking by TCNTn Write 18.5.3. Using the Output Compare Unit 18.6. Compare Match Output Unit 18.6.1. Compare Output Mode and Waveform Generation 18.7. Modes of Operation 18.7.1. Normal Mode 18.7.2. Clear Timer on Compare Match (CTC) Mode 18.7.3. Fast PWM Mode 18.7.4. Phase Correct PWM Mode 18.8. Timer/Counter Timing Diagrams 18.9. Register Description 18.9.1. TC0 Control Register A 18.9.2. TC0 Control Register B 18.9.3. TC0 Interrupt Mask Register 18.9.4. General Timer/Counter Control Register 18.9.5. TC0 Counter Value Register 18.9.6. TC0 Output Compare Register A 18.9.7. TC0 Output Compare Register B 18.9.8. TC0 Interrupt Flag Register 19. TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM 19.1. Features 19.2. Overview 19.2.1. Definitions 19.2.2. Registers 19.3. Accessing 16-bit Timer/Counter Registers 19.4. Timer/Counter Clock Sources 19.5. Counter Unit 19.6. Input Capture Unit 19.6.1. Input Capture Trigger Source 19.6.2. Noise Canceler 19.6.3. Using the Input Capture Unit 19.7. Compare Match Output Unit 19.7.1. Compare Output Mode and Waveform Generation 19.8. Output Compare Units 19.9. Modes of Operation 19.9.1. Normal Mode 19.9.2. Clear Timer on Compare Match (CTC) Mode 19.9.3. Fast PWM Mode 19.9.4. Phase Correct PWM Mode 19.9.5. Phase and Frequency Correct PWM Mode 19.10. Timer/Counter Timing Diagrams 19.11. Register Description 19.11.1. TC1 Control Register A 19.11.2. TC1 Control Register B 19.11.3. TC1 Control Register C 19.11.4. TC1 Counter Value Low and High byte 19.11.5. Input Capture Register 1 Low and High byte 19.11.6. Output Compare Register 1 A Low and High byte 19.11.7. Output Compare Register 1 B Low and High byte 19.11.8. TC3 Control Register A 19.11.9. TC3 Control Register B 19.11.10. TC3 Control Register C 19.11.11. TC3 Counter Value Low and High byte 19.11.12. Input Capture Register 3 Low and High byte 19.11.13. Output Compare Register 3 A Low and High byte 19.11.14. Output Compare Register 3 B Low and High byte 19.11.15. TC4 Control Register A 19.11.16. TC4 Control Register B 19.11.17. TC4 Control Register C 19.11.18. TC4 Counter Value Low and High byte 19.11.19. Input Capture Register 4 Low and High byte 19.11.20. Output Compare Register 4 A Low and High byte 19.11.21. Output Compare Register 4 B Low and High byte 19.11.22. Timer/Counter 1 Interrupt Mask Register 19.11.23. Timer/Counter 3 Interrupt Mask Register 19.11.24. Timer/Counter 4 Interrupt Mask Register 19.11.25. TC1 Interrupt Flag Register 19.11.26. TC3 Interrupt Flag Register 19.11.27. TC4 Interrupt Flag Register 20. Timer/Counter 0, 1, 3, 4 Prescalers 20.1. Internal Clock Source 20.2. Prescaler Reset 20.3. External Clock Source 20.4. Register Description 20.4.1. General Timer/Counter Control Register 21. TC2 - 8-bit Timer/Counter2 with PWM and Asynchronous Operation 21.1. Features 21.2. Overview 21.2.1. Definitions 21.2.2. Registers 21.3. Timer/Counter Clock Sources 21.4. Counter Unit 21.5. Output Compare Unit 21.5.1. Force Output Compare 21.5.2. Compare Match Blocking by TCNT2 Write 21.5.3. Using the Output Compare Unit 21.6. Compare Match Output Unit 21.6.1. Compare Output Mode and Waveform Generation 21.7. Modes of Operation 21.7.1. Normal Mode 21.7.2. Clear Timer on Compare Match (CTC) Mode 21.7.3. Fast PWM Mode 21.7.4. Phase Correct PWM Mode 21.8. Timer/Counter Timing Diagrams 21.9. Asynchronous Operation of Timer/Counter2 21.10. Timer/Counter Prescaler 21.11. Register Description 21.11.1. TC2 Control Register A 21.11.2. TC2 Control Register B 21.11.3. TC2 Counter Value Register 21.11.4. TC2 Output Compare Register A 21.11.5. TC2 Output Compare Register B 21.11.6. TC2 Interrupt Mask Register 21.11.7. TC2 Interrupt Flag Register 21.11.8. Asynchronous Status Register 21.11.9. General Timer/Counter Control Register 22. Output Compare Modulator (OCM1C2) 22.1. Overview 22.2. Description 22.2.1. Timing Example 23. SPI – Serial Peripheral Interface 23.1. Features 23.2. Overview 23.3. SS Pin Functionality 23.3.1. Slave Mode 23.3.2. Master Mode 23.4. Data Modes 23.5. Register Description 23.5.1. SPI Control Register 0 23.5.2. SPI Control Register 1 23.5.3. SPI Status Register 0 23.5.4. SPI Status Register 1 23.5.5. SPI Data Register 0 23.5.6. SPI Data Register 1 24. USART - Universal Synchronous Asynchronous Receiver Transceiver 24.1. Features 24.2. Overview 24.3. Block Diagram 24.4. Clock Generation 24.4.1. Internal Clock Generation – The Baud Rate Generator 24.4.2. Double Speed Operation (U2Xn) 24.4.3. External Clock 24.4.4. Synchronous Clock Operation 24.5. Frame Formats 24.5.1. Parity Bit Calculation 24.6. USART Initialization 24.7. Data Transmission – The USART Transmitter 24.7.1. Sending Frames with 5 to 8 Data Bits 24.7.2. Sending Frames with 9 Data Bits 24.7.3. Transmitter Flags and Interrupts 24.7.4. Parity Generator 24.7.5. Disabling the Transmitter 24.8. Data Reception – The USART Receiver 24.8.1. Receiving Frames with 5 to 8 Data Bits 24.8.2. Receiving Frames with 9 Data Bits 24.8.3. Receive Compete Flag and Interrupt 24.8.4. Receiver Error Flags 24.8.5. Parity Checker 24.8.6. Disabling the Receiver 24.8.7. Flushing the Receive Buffer 24.9. Asynchronous Data Reception 24.9.1. Asynchronous Clock Recovery 24.9.2. Asynchronous Data Recovery 24.9.3. Asynchronous Operational Range 24.9.4. Start Frame Detection 24.10. Multi-Processor Communication Mode 24.10.1. Using MPCMn 24.11. Examples of Baud Rate Setting 24.12. Register Description 24.12.1. USART I/O Data Register n 24.12.2. USART Control and Status Register n A 24.12.3. USART Control and Status Register n B 24.12.4. USART Control and Status Register n C 24.12.5. USART Baud Rate n Register Low and High byte 25. USARTSPI - USART in SPI Mode 25.1. Features 25.2. Overview 25.3. Clock Generation 25.4. SPI Data Modes and Timing 25.5. Frame Formats 25.5.1. USART MSPIM Initialization 25.6. Data Transfer 25.6.1. Transmitter and Receiver Flags and Interrupts 25.6.2. Disabling the Transmitter or Receiver 25.7. AVR USART MSPIM vs. AVR SPI 25.8. Register Description 26. TWI - Two-Wire Serial Interface 26.1. Features 26.2. Two-Wire Serial Interface Bus Definition 26.2.1. TWI Terminology 26.2.2. Electrical Interconnection 26.3. Data Transfer and Frame Format 26.3.1. Transferring Bits 26.3.2. START and STOP Conditions 26.3.3. Address Packet Format 26.3.4. Data Packet Format 26.3.5. Combining Address and Data Packets Into a Transmission 26.4. Multi-Master Bus Systems, Arbitration, and Synchronization 26.5. Overview of the TWI Module 26.5.1. SCL and SDA Pins 26.5.2. Bit Rate Generator Unit 26.5.3. Bus Interface Unit 26.5.4. Address Match Unit 26.5.5. Control Unit 26.6. Using the TWI 26.7. Transmission Modes 26.7.1. Master Transmitter Mode 26.7.2. Master Receiver Mode 26.7.3. Slave Transmitter Mode 26.7.4. Slave Receiver Mode 26.7.5. Miscellaneous States 26.7.6. Combining Several TWI Modes 26.8. Multi-Master Systems and Arbitration 26.9. Register Description 26.9.1. TWI n Bit Rate Register 26.9.2. TWI Status Register n 26.9.3. TWI (Slave) Address Register n 26.9.4. TWI Data Register n 26.9.5. TWI Control Register n 26.9.6. TWI (Slave) Address Mask Register n 27. AC - Analog Comparator 27.1. Overview 27.2. Analog Comparator Multiplexed Input 27.3. Register Description 27.3.1. Analog Comparator Control and Status Register 27.3.2. Digital Input Disable Register 1 28. ADC - Analog-to-Digital Converter 28.1. Features 28.2. Overview 28.3. Starting a Conversion 28.4. Prescaling and Conversion Timing 28.5. Changing Channel or Reference Selection 28.5.1. ADC Input Channels 28.5.2. ADC Voltage Reference 28.6. ADC Noise Canceler 28.6.1. Analog Input Circuitry 28.6.2. Analog Noise Canceling Techniques 28.6.3. ADC Accuracy Definitions 28.7. ADC Conversion Result 28.8. Temperature Measurement 28.9. Register Description 28.9.1. ADC Multiplexer Selection Register 28.9.2. ADC Control and Status Register A 28.9.3. ADC Data Register Low and High Byte (ADLAR=0) 28.9.4. ADC Data Register Low and High Byte (ADLAR=1) 28.9.5. ADC Control and Status Register B 28.9.6. Digital Input Disable Register 0 29. PTC - Peripheral Touch Controller 29.1. Features 29.2. Overview 29.3. Block Diagram 29.4. Signal Description 29.5. Product Dependencies 29.5.1. I/O Lines 29.5.1.1. Mutual-Capacitance Sensor Arrangement 29.5.1.2. Self-Capacitance Sensor Arrangement 29.6. Functional Description 30. debugWIRE On-chip Debug System 30.1. Features 30.2. Overview 30.3. Physical Interface 30.4. Software Breakpoints 30.5. Limitations of debugWIRE 30.6. Register Description 30.6.1. debugWire Data Register 31. BTLDR - Boot Loader Support – Read-While-Write Self-Programming 31.1. Features 31.2. Overview 31.3. Application and Boot Loader Flash Sections 31.3.1. Application Section 31.3.2. BLS – Boot Loader Section 31.4. Read-While-Write and No Read-While-Write Flash Sections 31.4.1. RWW – Read-While-Write Section 31.4.2. NRWW – No Read-While-Write Section 31.5. Entering the Boot Loader Program 31.6. Boot Loader Lock Bits 31.7. Addressing the Flash During Self-Programming 31.8. Self-Programming the Flash 31.8.1. Performing Page Erase by SPM 31.8.2. Filling the Temporary Buffer (Page Loading) 31.8.3. Performing a Page Write 31.8.4. Using the SPM Interrupt 31.8.5. Consideration While Updating Boot Loader Section (BLS) 31.8.6. Prevent Reading the RWW Section During Self-Programming 31.8.7. Setting the Boot Loader Lock Bits by SPM 31.8.8. EEPROM Write Prevents Writing to SPMCSR 31.8.9. Reading the Fuse and Lock Bits from Software 31.8.10. Reading the Signature Row from Software 31.8.11. Preventing Flash Corruption 31.8.12. Programming Time for Flash when Using SPM 31.8.13. Simple Assembly Code Example for a Boot Loader 31.8.14. Boot Loader Parameters 31.9. Register Description 31.9.1. SPMCSR – Store Program Memory Control and Status Register 32. MEMPROG - Memory Programming 32.1. Program And Data Memory Lock Bits 32.2. Fuse Bits 32.2.1. Latching of Fuses 32.3. Signature Bytes 32.4. Calibration Byte 32.5. Serial Number 32.5.1. Signature Row Summary - SIGROW 32.5.1.1. Device ID n 32.5.1.2. RC Oscillator Calibration Byte 32.5.1.3. Serial Number Byte n 32.6. Page Size 32.7. Parallel Programming Parameters, Pin Mapping, and Commands 32.7.1. Signal Names 32.8. Parallel Programming 32.8.1. Entering Programming Mode 32.8.2. Considerations for Efficient Programming 32.8.3. Chip Erase 32.8.4. Programming the Flash 32.8.5. Programming the EEPROM 32.8.6. Reading the Flash 32.8.7. Reading the EEPROM 32.8.8. Programming the Fuse Low Bits 32.8.9. Programming the Fuse High Bits 32.8.10. Programming the Extended Fuse Bits 32.8.11. Programming the Lock Bits 32.8.12. Reading the Fuse and Lock Bits 32.8.13. Reading the Signature Bytes 32.8.14. Reading the Calibration Byte 32.8.15. Parallel Programming Characteristics 32.9. Serial Downloading 32.9.1. Serial Programming Pin Mapping 32.9.2. Serial Programming Algorithm 32.9.3. Serial Programming Instruction Set 32.9.4. SPI Serial Programming Characteristics 33. Electrical Characteristics 33.1. Absolute Maximum Ratings* 33.2. DC Characteristics 33.3. Power Consumption 33.4. Speed Grades 33.5. Clock Characteristics 33.5.1. Calibrated Internal RC Oscillator Accuracy 33.5.2. External Clock Drive Waveforms 33.5.3. External Clock Drive 33.6. System and Reset Characteristics 33.7. SPI Timing Characteristics 33.8. Two-wire Serial Interface Characteristics 33.9. ADC Characteristics 33.10. Parallel Programming Characteristics 34. Typical Characteristics 34.1. Active Supply Current 34.2. Idle Supply Current 34.3. ATmega328PB Supply Current of I/O Modules 34.4. Power-Down Supply Current 34.5. Pin Pull-Up 34.6. Pin Driver Strength 34.7. Pin Threshold and Hysteresis 34.8. BOD Threshold 34.9. Analog Comparator Offset 34.10. Internal Oscillator Speed 34.11. Current Consumption of Peripheral Units 34.12. Current Consumption in Reset and Reset Pulse Width 35. Register Summary 36. Instruction Set Summary 37. Packaging Information 37.1. 32A 37.2. 32-Pin VQFN 38. Errata 38.1. Rev. A 38.2. Rev. B 38.3. Rev. C - D 38.4. Rev. A - D 39. Revision History The Microchip Web Site Customer Change Notification Service Customer Support Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Certified by DNV Worldwide Sales and Service