The UART Baud Rate Generator (BRG) is a 16-bit timer used to generate the clocking mechanism required for communication. The timer consists of the UART Baud Rate Generator High and Low register pair (UxBRGH:UxBRGL). The Baud Rate Generator Speed Select (BRGS) bit of UxCON0 determines the number of baud clocks used per bit.
When BRGS is clear (BRGS = 0), the BRG is configured in the
normal baud rate range. In the normal baud rate range, the BRG generates 16 clock periods per
data bit. Equation 1-1 shows the formula used to calculate the baud rate when BRGS is clear.
The result of this formula should be loaded into the UxBRGH:UxBRGL register pair.
0)
1)
Writing to the UxBRGH:UxBRGL register pair will immediately change the baud rate.
If the register pair is written while the module is actively transmitting or receiving data, a
receive error may occur. It is recommended that writes to the register pair occur when the
Receive Pin Idle Status (RXIDL) bit of UxFIFO is set (RXIDL = 1), indicating
an Idle condition. Additionally, if the system clock (FOSC) is changed during
active communication, a receive error may occur.
It is important to note that the BRG relies on the system clock (FOSC) to generate the baud rate. If the system clock deviates from its frequency (due to noise, temperature, oscillator drift, etc.), the baud rate will also change, resulting in framing or overrun errors. The Auto-Baud Detection feature can be used to ensure that the bit rate is acceptable for error-free communication.