Overview

The UART module is a core-independent peripheral that performs serial data transfers without any CPU intervention. The module includes the following features:

Full-Duplex Transmit and Receive
Two-Character Input Buffer
One-Character Output Buffer
Programmable 7-Bit or 8-Bit Character Length
9th Bit Address Detection
9th Bit Parity
Input Buffer Overrun Detection
Framing Error Detection
Hardware and Software Flow Control
Automatic Checksums
Programmable Stop Bit Count
Programmable Data Polarity
Automatic Detection and Calibration of the Baud Rate
Operation in Sleep
Wake-Up on Break Reception
Automatic and User-Timed Break Period Generation
Inactivity Time-Outs

The UART module transmits and receives data using the standard Non-Return-to-Zero (NRZ) format. The NRZ format uses two logic states, V_OH and V_OL. The V_OH Mark state represents a ‘1’ data bit, while the V_OL Space state represents a ‘0’ data bit. The NRZ format states that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to the neutral level between bits (Figure 1). An NRZ transmission port idles in the Mark (‘1’) state. Each character transmission consists of a Start bit, followed by seven or eight data bits, one optional parity or address bit, and ends with one or more Stop bits. The Start bit is always a space (‘0’), while Stop bits are always marks (‘1’). The most common data format consists of eight data bits and no parity bit.

Figure 1. NRZ Format

UART Mode Select Bits (MODE<3:0> bits of the UxCON0 register):

0100 = Asynchronous 9-bit UART Address mode. 9th bit 1 = address; 0 = data
0011 = Asynchronous 8-bit UART mode with 9th bit even parity
0010 = Asynchronous 8-bit UART mode with 9th bit odd parity
0001 = Asynchronous 7-bit UART mode
0001 = Asynchronous 7-bit UART mode
0000 = Asynchronous 8-bit UART mode

The UART module transmits and receives the Least Significant bit (LSb) first, regardless of which mode is selected. Both transmitter and receiver blocks operate independently, but share the same baud rate and data format. A dedicated 16-bit Baud Rate Generator (BRG) derives the baud rate from the system oscillator. Each transmitted bit persists for a period of 1/Baud Rate.