XDMAC Channel x Configuration Register [x = 0..23]
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PERID[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WRIP | RDIP | INITD | DAM[1:0] | SAM[1:0] | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DIF | SIF | DWIDTH[1:0] | CSIZE[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MEMSET | SWREQ | DSYNC | MBSIZE[1:0] | TYPE | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Channel x Transfer Type
0 (MEM_TRAN): Self-triggered mode (memory-to-memory transfer).
1 (PER_TRAN): Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
Channel x Memory Burst Size
| Value | Name | Description |
|---|---|---|
| 0 | SINGLE | The memory burst size is set to one. |
| 1 | FOUR | The memory burst size is set to four. |
| 2 | EIGHT | The memory burst size is set to eight. |
| 3 | SIXTEEN | The memory burst size is set to sixteen. |
Channel x Synchronization
0 (PER2MEM): Peripheral-to-memory transfer.
1 (MEM2PER): Memory-to-peripheral transfer.
Channel x Software Request Trigger
0 (HWR_CONNECTED): Hardware request line is connected to the peripheral request line.
1 (SWR_CONNECTED): Software request is connected to the peripheral request line.
Channel x Fill Block of Memory
0 (NORMAL_MODE): Memset is not activated.
1 (HW_MODE): Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.
Channel x Chunk Size
| Value | Name | Description |
|---|---|---|
| 0 | CHK_1 | 1 data transferred |
| 1 | CHK_2 | 2 data transferred |
| 2 | CHK_4 | 4 data transferred |
| 3 | CHK_8 | 8 data transferred |
| 4 | CHK_16 | 16 data transferred |
Channel x Data Width
| Value | Name | Description |
|---|---|---|
| 0 | BYTE | The data size is set to 8 bits |
| 1 | HALFWORD | The data size is set to 16 bits |
| 2 | WORD | The data size is set to 32 bits |
Channel x Source Interface Identifier
0 (AHB_IF0): The data is read through system bus interface 0.
1 (AHB_IF1): The data is read through system bus interface 1.
Channel x Destination Interface Identifier
0 (AHB_IF0): The data is written through system bus interface 0.
1 (AHB_IF1): The data is written though system bus interface 1.
Channel x Source Addressing Mode
| Value | Name | Description |
|---|---|---|
| 0 | FIXED_AM | The address remains unchanged. |
| 1 | INCREMENTED_AM | The addressing mode is incremented (the increment size is set to the data size). |
| 2 | UBS_AM | The microblock stride is added at the microblock boundary. |
| 3 | UBS_DS_AM | The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. |
Channel x Destination Addressing Mode
| Value | Name | Description |
|---|---|---|
| 0 | FIXED_AM | The address remains unchanged. |
| 1 | INCREMENTED_AM | The addressing mode is incremented (the increment size is set to the data size). |
| 2 | UBS_AM | The microblock stride is added at the microblock boundary. |
| 3 | UBS_DS_AM | The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. |
Channel Initialization Done (this bit is read-only)
0 (IN_PROGRESS): Channel initialization is in progress.
1 (TERMINATED): Channel initialization is completed.
Note: When set to 0, XDMAC_CUBC.UBLEN and XDMAC_CNDA.NDA field values are unreliable each time a descriptor is being updated. See XDMAC Software Requirements.
Read in Progress (this bit is read-only)
0 (DONE): No active read transaction on the bus.
1 (IN_PROGRESS): A read transaction is in progress.
Write in Progress (this bit is read-only)
0 (DONE): No active write transaction on the bus.
1 (IN_PROGRESS): A write transaction is in progress.
Channel x Peripheral Hardware Request Line Identifier
This field contains the peripheral hardware request line identifier. PERID refers to identifiers defined in “DMA Controller Peripheral Connections”.