ISI_IMR

ISI Interrupt Mask Register

  0x34 32 Read-only 0x00000000  
Parent topic: Register Summary

ISI Interrupt Mask Register

Bit  31 30 29 28 27 26 25 24  
          FR_OVR CRC_ERR C_OVR P_OVR  
Access          R R R R  
Reset          0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
              CXFR_DONE PXFR_DONE  
Access              R R  
Reset              0 0  
Bit  15 14 13 12 11 10 9 8  
            VSYNC      
Access            R      
Reset            0      
Bit  7 6 5 4 3 2 1 0  
            SRST DIS_DONE    
Access            R R    
Reset            0 0    

Bit 1 – DIS_DONE: Module Disable Operation Completed

Module Disable Operation Completed

ValueDescription
0

The Module Disable Operation Completed interrupt is disabled.
1

The Module Disable Operation Completed interrupt is enabled.

Bit 2 – SRST: Software Reset Completed

Software Reset Completed

ValueDescription
0

The Software Reset Completed interrupt is disabled.
1

The Software Reset Completed interrupt is enabled.

Bit 10 – VSYNC: Vertical Synchronization

Vertical Synchronization

ValueDescription
0

The Vertical Synchronization interrupt is disabled.
1

The Vertical Synchronization interrupt is enabled.

Bit 16 – PXFR_DONE: Preview DMA Transfer Completed

Preview DMA Transfer Completed

ValueDescription
0

The Preview DMA Transfer Completed interrupt is disabled.
1

The Preview DMA Transfer Completed interrupt is enabled.

Bit 17 – CXFR_DONE: Codec DMA Transfer Completed

Codec DMA Transfer Completed

ValueDescription
0

The Codec DMA Transfer Completed interrupt is disabled.
1

The Codec DMA Transfer Completed interrupt is enabled.

Bit 24 – P_OVR: Preview FIFO Overflow

Preview FIFO Overflow

ValueDescription
0

The Preview FIFO Overflow interrupt is disabled.
1

The Preview FIFO Overflow interrupt is enabled.

Bit 25 – C_OVR: Codec FIFO Overflow

Codec FIFO Overflow

ValueDescription
0

The Codec FIFO Overflow interrupt is disabled.
1

The Codec FIFO Overflow interrupt is enabled.

Bit 26 – CRC_ERR: CRC Synchronization Error

CRC Synchronization Error

ValueDescription
0

The CRC Synchronization Error interrupt is disabled.
1

The CRC Synchronization Error interrupt is enabled.

Bit 27 – FR_OVR: Frame Rate Overrun

Frame Rate Overrun

ValueDescription
0

The Frame Rate Overrun interrupt is disabled.
1

The Frame Rate Overrun is enabled.