USART Mode Register (SPI_MODE)
This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
– Applicable if USART operates in SPI mode (USART_MODE = 0xE or 0xF):
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WRDBT | CLKO | CPOL | |||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CPHA | |||||||||
| Access | |||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHRL[1:0] | USCLKS[1:0] | USART_MODE[3:0] | |||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
USART Mode of Operation
| Value | Name | Description |
|---|---|---|
| 0xE | SPI_MASTER | SPI master |
| 0xF | SPI_SLAVE | SPI Slave |
Clock Selection
| Value | Name | Description |
|---|---|---|
| 0 | MCK | Peripheral clock is selected |
| 1 | DIV | Peripheral clock divided (DIV=DIV=8) is selected |
| 3 | SCK | Serial Clock (SCK) is selected |
Character Length
| Value | Name | Description |
|---|---|---|
| 3 | 8_BIT | Character length is 8 bits |
SPI Clock Phase
CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used with CPOL to produce the required clock/data relationship between master and slave devices.
| Value | Description |
|---|---|
| 0 | Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. |
| 1 | Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. |
SPI Clock Polarity
Applicable if USART operates in SPI mode (Slave or Master, USART_MODE = 0xE or 0xF):
CPOL is used to determine the inactive state value of the serial clock (SCK). It is used with CPHA to produce the required clock/data relationship between master and slave devices.
| Value | Description |
|---|---|
| 0 | The inactive state value of SPCK is logic level zero. |
| 1 | The inactive state value of SPCK is logic level one. |
Clock Output Select
| Value | Description |
|---|---|
| 0 | The USART does not drive the SCK pin. |
| 1 | The USART drives the SCK pin if USCLKS does not select the external clock SCK. |
Wait Read Data Before Transfer
| Value | Description |
|---|---|
| 0 | The character transmission starts as soon as a character is written into US_THR (assuming TXRDY was set). |
| 1 | The character transmission starts when a character is written and only if RXRDY flag is cleared (Receive Holding Register has been read). |