PLL Maximum Multiplier Value Register
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PLLA_MMAX[10:8] | |||||||||
| Access | |||||||||
| Reset | 1 | 1 | 1 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PLLA_MMAX[7:0] | |||||||||
| Access | |||||||||
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
PLLA Maximum Allowed Multiplier Value
Defines the maximum value of multiplication factor that can be sent to PLLA. Any value of the MULA field (see PMC Clock Generator PLLA Register) above PLLA_MMAX is saturated to PLLA_MMAX. PLLA_MMAX write operation is cancelled in the following cases:
• The value of MULA is currently saturated by PLLA_MMAX
• The user is trying to write a value of PLLA_MMAX that is smaller than the current value of MULA