TC_CMRx

TC Channel Mode Register: Capture Mode

This register can be written only if the WPEN bit is cleared in the TC Write Protection Mode Register.

  0x04 + x*0x40 [x=0..2] 32 Read/Write 0x00000000   3 64 -1
Parent topic: Register Summary

TC Channel Mode Register: Capture Mode

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
    SBSMPLR[2:0] LDRB[1:0] LDRA[1:0]  
Access    R/W R/W R/W R/W R/W R/W R/W  
Reset    0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  WAVE CPCTRG       ABETRG ETRGEDG[1:0]  
Access  R/W R/W       R/W R/W R/W  
Reset  0 0       0 0 0  
Bit  7 6 5 4 3 2 1 0  
  LDBDIS LDBSTOP BURST[1:0] CLKI TCCLKS[2:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 2:0 – TCCLKS[2:0]: Clock Selection

Clock Selection

To operate at maximum peripheral clock frequency, refer to “TC Extended Mode Register”.

ValueNameDescription
0 TIMER_CLOCK1 Clock selected: internal PCK6 or PCK7 (TC0 only) clock signal (from PMC)
1 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC)
2 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC)
3 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC)
4 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC)
5 XC0 Clock selected: XC0
6 XC1 Clock selected: XC1
7 XC2 Clock selected: XC2

Bit 3 – CLKI: Clock Invert

Clock Invert

ValueDescription
0 Counter is incremented on rising edge of the clock.
1 Counter is incremented on falling edge of the clock.

Bits 5:4 – BURST[1:0]: Burst Signal Selection

Burst Signal Selection

ValueNameDescription
0 NONE The clock is not gated by an external signal.
1 XC0 XC0 is ANDed with the selected clock.
2 XC1 XC1 is ANDed with the selected clock.
3 XC2 XC2 is ANDed with the selected clock.

Bit 6 – LDBSTOP: Counter Clock Stopped with RB Loading

Counter Clock Stopped with RB Loading

ValueDescription
0 Counter clock is not stopped when RB loading occurs.
1 Counter clock is stopped when RB loading occurs.

Bit 7 – LDBDIS: Counter Clock Disable with RB Loading

Counter Clock Disable with RB Loading

ValueDescription
0 Counter clock is not disabled when RB loading occurs.
1 Counter clock is disabled when RB loading occurs.

Bits 9:8 – ETRGEDG[1:0]: External Trigger Edge Selection

External Trigger Edge Selection

ValueNameDescription
0 NONE The clock is not gated by an external signal.
1 RISING Rising edge
2 FALLING Falling edge
3 EDGE Each edge

Bit 10 – ABETRG: TIOAx or TIOBx External Trigger Selection

TIOAx or TIOBx External Trigger Selection

ValueDescription
0 TIOBx is used as an external trigger.
1 TIOAx is used as an external trigger.

Bit 14 – CPCTRG: RC Compare Trigger Enable

RC Compare Trigger Enable

ValueDescription
0 RC Compare has no effect on the counter and its clock.
1 RC Compare resets the counter and starts the counter clock.

Bit 15 – WAVE: Waveform Mode

Waveform Mode

ValueDescription
0 Capture mode is enabled.
1 Capture mode is disabled (Waveform mode is enabled).

Bits 17:16 – LDRA[1:0]: RA Loading Edge Selection

RA Loading Edge Selection

ValueNameDescription
0 NONE None
1 RISING Rising edge of TIOAx
2 FALLING Falling edge of TIOAx
3 EDGE Each edge of TIOAx

Bits 19:18 – LDRB[1:0]: RB Loading Edge Selection

RB Loading Edge Selection

ValueNameDescription
0 NONE None
1 RISING Rising edge of TIOAx
2 FALLING Falling edge of TIOAx
3 EDGE Each edge of TIOAx

Bits 22:20 – SBSMPLR[2:0]: Loading Edge Subsampling Ratio

Loading Edge Subsampling Ratio

ValueNameDescription
0 ONE Load a Capture register each selected edge.
1 HALF Load a Capture register every 2 selected edges.
2 FOURTH Load a Capture register every 4 selected edges.
3 EIGHTH Load a Capture register every 8 selected edges.
4 SIXTEENTH Load a Capture register every 16 selected edges.