USBHS_HSTPIPIDRx (ISOPIPES)

Host Pipe x Disable Register (Isochronous Pipes)

This register view is relevant only if PTYPE = 0x1 in ”Host Pipe x Configuration Register”.

For additional information, see ”Host Pipe x Mask Register (Isochronous Pipes)”.

This register always reads as zero.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Clears the corresponding bit in USBHS_HSTPIPIMRx.

  0x0620 + x*0x04 [x=0..9] 32 Read/Write 0   10 x
Parent topic: Register Summary

Host Pipe x Disable Register (Isochronous Pipes)

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
              PFREEZEC PDISHDMAC  
Access                   
Reset              0 0  
Bit  15 14 13 12 11 10 9 8  
    FIFOCONC   NBUSYBKEC          
Access                   
Reset    0   0          
Bit  7 6 5 4 3 2 1 0  
  SHORTPACKETIEC CRCERREC OVERFIEC NAKEDEC PERREC UNDERFIEC TXOUTEC RXINEC  
Access                   
Reset  0 0 0 0 0 0 0 0  

Bit 0 – RXINEC: Received IN Data Interrupt Disable

Received IN Data Interrupt Disable

Bit 1 – TXOUTEC: Transmitted OUT Data Interrupt Disable

Transmitted OUT Data Interrupt Disable

Bit 2 – UNDERFIEC: Underflow Interrupt Disable

Underflow Interrupt Disable

Bit 3 – PERREC: Pipe Error Interrupt Disable

Pipe Error Interrupt Disable

Bit 4 – NAKEDEC: NAKed Interrupt Disable

NAKed Interrupt Disable

Bit 5 – OVERFIEC: Overflow Interrupt Disable

Overflow Interrupt Disable

Bit 6 – CRCERREC: CRC Error Interrupt Disable

CRC Error Interrupt Disable

Bit 7 – SHORTPACKETIEC: Short Packet Interrupt Disable

Short Packet Interrupt Disable

Bit 12 – NBUSYBKEC: Number of Busy Banks Disable

Number of Busy Banks Disable

Bit 14 – FIFOCONC: FIFO Control Disable

FIFO Control Disable

Bit 16 – PDISHDMAC: Pipe Interrupts Disable HDMA Request Disable

Pipe Interrupts Disable HDMA Request Disable

Bit 17 – PFREEZEC: Pipe Freeze Disable

Pipe Freeze Disable