USBHS_HSTPIPIMRx (INTPIPES)

Host Pipe x Mask Register (Interrupt Pipes)

This register view is relevant only if PTYPE = 0x3 in ”Host Pipe x Configuration Register”.

  0x05C0 + x*0x04 [x=0..9] 32 Read/Write 0   10 x
Parent topic: Register Summary

Host Pipe x Mask Register (Interrupt Pipes)

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
            RSTDT PFREEZE PDISHDMA  
Access                   
Reset            0 0 0  
Bit  15 14 13 12 11 10 9 8  
    FIFOCON   NBUSYBKE          
Access                   
Reset    0   0          
Bit  7 6 5 4 3 2 1 0  
  SHORTPACKETIE RXSTALLDE OVERFIE NAKEDE PERRE UNDERFIE TXOUTE RXINE  
Access                   
Reset  0 0 0 0 0 0 0 0  

Bit 0 – RXINE: Received IN Data Interrupt Enable

Received IN Data Interrupt Enable

ValueDescription
0

Cleared when USBHS_HSTPIPIDR.RXINEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.RXINE).
1

Set when USBHS_HSTPIPIER.RXINES= 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.RXINE).

Bit 1 – TXOUTE: Transmitted OUT Data Interrupt Enable

Transmitted OUT Data Interrupt Enable

ValueDescription
0

Cleared when USBHS_HSTPIPIDR.TXOUTEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.TXOUTE).
1

Set when USBHS_HSTPIPIER.TXOUTES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.TXOUTE).

Bit 2 – UNDERFIE: Underflow Interrupt Enable

Underflow Interrupt Enable

ValueDescription
0

Cleared when USBHS_HSTPIPIDR.UNDERFIEC= 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.UNDERFIE).
1

Set when USBHS_HSTPIPIER.UNDERFIES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.UNDERFIE).

Bit 3 – PERRE: Pipe Error Interrupt Enable

Pipe Error Interrupt Enable

ValueDescription
0

Cleared when USBHS_HSTPIPIDR.PERREC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.PERRE).
1

Set when USBHS_HSTPIPIER.PERRES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.PERRE).

Bit 4 – NAKEDE: NAKed Interrupt Enable

NAKed Interrupt Enable

ValueDescription
0

Cleared when USBHS_HSTPIPIDR.NAKEDEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.NAKEDE).
1

Set when USBHS_HSTPIPIER.NAKEDES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.NAKEDE).

Bit 5 – OVERFIE: Overflow Interrupt Enable

Overflow Interrupt Enable

ValueDescription
0

Cleared when USBHS_HSTPIPIDR.OVERFIEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.OVERFIE).
1

Set when USBHS_HSTPIPIER.OVERFIES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.OVERFIE).

Bit 6 – RXSTALLDE: Received STALLed Interrupt Enable

Received STALLed Interrupt Enable

ValueDescription
0

Cleared when USBHS_HSTPIPIDR.RXSTALLDEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.RXSTALLDE).
1

Set when USBHS_HSTPIPIER.RXSTALLDES= 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.RXSTALLDE).

Bit 7 – SHORTPACKETIE: Short Packet Interrupt Enable

Short Packet Interrupt Enable

If this bit is set for non-control OUT pipes, a short packet transmission is guaranteed upon ending a DMA transfer, thus signaling an end of transfer, provided that the End of DMA Buffer Output Enable (USBHS_HSTDMACONTROL.END_B_EN) bit and the Automatic Switch (USBHS_HSTPIPCFG.AUTOSW) bit = 1.

ValueDescription
0

Cleared when USBHS_HSTPIPIDR.SHORTPACKETEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.SHORTPACKETE).
1

Set when USBHS_HSTPIPIER.SHORTPACKETIES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.SHORTPACKETIE).

Bit 12 – NBUSYBKE: Number of Busy Banks Interrupt Enable

Number of Busy Banks Interrupt Enable

ValueDescription
0

Cleared when USBHS_HSTPIPIDR.NBUSYBKEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.NBUSYBKE).
1

Set when USBHS_HSTPIPIER.NBUSYBKES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.NBUSYBKE).

Bit 14 – FIFOCON: FIFO Control

FIFO Control

For OUT and SETUP pipes:

0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1. This sends the FIFO data and switches the bank.

1: Set when the current bank is free, at the same time as USBHS_HSTPIPISR.TXOUTI or TXSTPI.

For IN pipes:

0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1. This frees the current bank and switches to the next bank.

1: Set when a new IN message is stored in the current bank, at the same time as USBHS_HSTPIPISR.RXINI.

Bit 16 – PDISHDMA: Pipe Interrupts Disable HDMA Request Enable

Pipe Interrupts Disable HDMA Request Enable

See the USBHS_DEVEPTIMR.EPDISHDMA bit description.

Bit 17 – PFREEZE: Pipe Freeze

Pipe Freeze

This freezes the pipe request generation.

ValueDescription
0

Cleared when USBHS_HSTPIPIDR.PFREEZEC = 1. This enables the pipe request generation.
1

Set when one of the following conditions is met:

• USBHS_HSTPIPIER.PFREEZES = 1

• The pipe is not configured.

• A STALL handshake has been received on the pipe.

• An error has occurred on the pipe (USBHS_HSTPIPISR.PERRI = 1).

• (INRQ+1) in requests have been processed.

• A Pipe Reset (USBHS_HSTPIP.PRSTx rising) has occurred.

• A Pipe Enable (USBHS_HSTPIP.PEN rising) has occurred.

Bit 18 – RSTDT: Reset Data Toggle

Reset Data Toggle

ValueDescription
0

0: No reset of the Data Toggle is ongoing.
1

Set when USBHS_HSTPIPIER.RSTDTS = 1. This resets the Data Toggle to its initial value for the current pipe.