USBHS_DEVEPTICRx

Device Endpoint Interrupt Clear Register (Control, Bulk, Interrupt Endpoints)

This register view is relevant only if EPTYPE = 0x0, 0x2, or 0x3 in the ”Device Endpoint x Configuration Register”.

For additional information, see ”Device Endpoint x Status Register (Control, Bulk, Interrupt Endpoints)”.

This register always reads as zero.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Clears the corresponding bit in USBHS_DEVEPTISRx.

  0x0160 + x*0x04 [x=0..9] 32 Read/Write 0   10 x
Parent topic: Register Summary

Device Endpoint Interrupt Clear Register (Control, Bulk, Interrupt Endpoints)

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
  SHORTPACKETC STALLEDIC OVERFIC NAKINIC NAKOUTIC RXSTPIC RXOUTIC TXINIC  
Access                   
Reset  0 0 0 0 0 0 0 0  

Bit 0 – TXINIC: Transmitted IN Data Interrupt Clear

Transmitted IN Data Interrupt Clear

Bit 1 – RXOUTIC: Received OUT Data Interrupt Clear

Received OUT Data Interrupt Clear

Bit 2 – RXSTPIC: Received SETUP Interrupt Clear

Received SETUP Interrupt Clear

Bit 3 – NAKOUTIC: NAKed OUT Interrupt Clear

NAKed OUT Interrupt Clear

Bit 4 – NAKINIC: NAKed IN Interrupt Clear

NAKed IN Interrupt Clear

Bit 5 – OVERFIC: Overflow Interrupt Clear

Overflow Interrupt Clear

Bit 6 – STALLEDIC: STALLed Interrupt Clear

STALLed Interrupt Clear

Bit 7 – SHORTPACKETC: Short Packet Interrupt Clear

Short Packet Interrupt Clear