US_CSR (SPI_MODE)

USART Channel Status Register (SPI_MODE)

This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.

  0x0014 32 Read-only 0x0  

USART Channel Status Register (SPI_MODE)

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
  NSS       NSSE        
Access                   
Reset  0       0        
Bit  15 14 13 12 11 10 9 8  
            UNRE TXEMPTY    
Access                   
Reset            0 0    
Bit  7 6 5 4 3 2 1 0  
      OVRE       TXRDY RXRDY  
Access                   
Reset      0       0 0  

Bit 0 – RXRDY: Receiver Ready (cleared by reading US_RHR)

Receiver Ready (cleared by reading US_RHR)

ValueDescription
0

No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.

1

At least one complete character has been received and US_RHR has not yet been read.

Bit 1 – TXRDY: Transmitter Ready (cleared by writing US_THR)

Transmitter Ready (cleared by writing US_THR)

ValueDescription
0

A character is in the US_THR waiting to be transferred to the Transmit Shift Register or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.

1

There is no character in the US_THR.

Bit 5 – OVRE: Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)

Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)

ValueDescription
0

No overrun error has occurred since the last RSTSTA.

1

At least one overrun error has occurred since the last RSTSTA.

Bit 9 – TXEMPTY: Transmitter Empty (cleared by writing US_THR)

Transmitter Empty (cleared by writing US_THR)

ValueDescription
0

There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.

1

There are no characters in US_THR, nor in the Transmit Shift Register.

Bit 10 – UNRE: Underrun Error (cleared by writing a one to bit US_CR.RSTSTA)

Underrun Error (cleared by writing a one to bit US_CR.RSTSTA)

ValueDescription
0

No SPI underrun error has occurred since the last RSTSTA.

1

At least one SPI underrun error has occurred since the last RSTSTA.

Bit 19 – NSSE: NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read)

NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read)

ValueDescription
0

No NSS line event has been detected since the last read of US_CSR.

1

A rising or falling edge event has been detected on NSS line since the last read of US_CSR.

Bit 23 – NSS: Image of NSS Line

Image of NSS Line

ValueDescription
0

NSS line is driven low (if NSSE = 1, falling edge occurred on NSS line).

1

NSS line is driven high (if NSSE = 1, rising edge occurred on NSS line).