SSC_IDR

SSC Interrupt Disable Register

  0x48 32 Write-only –  
Parent topic: Register Summary

SSC Interrupt Disable Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
          RXSYN TXSYN CP1 CP0  
Access          W W W W  
Reset          – – – –  
Bit  7 6 5 4 3 2 1 0  
      OVRUN RXRDY     TXEMPTY TXRDY  
Access      W W     W W  
Reset      – –     – –  

Bit 0 – TXRDY: Transmit Ready Interrupt Disable

Transmit Ready Interrupt Disable

ValueDescription
0

No effect.
1

Disables the Transmit Ready Interrupt.

Bit 1 – TXEMPTY: Transmit Empty Interrupt Disable

Transmit Empty Interrupt Disable

ValueDescription
0

No effect.
1

Disables the Transmit Empty Interrupt.

Bit 4 – RXRDY: Receive Ready Interrupt Disable

Receive Ready Interrupt Disable

ValueDescription
0

No effect.
1

Disables the Receive Ready Interrupt.

Bit 5 – OVRUN: Receive Overrun Interrupt Disable

Receive Overrun Interrupt Disable

ValueDescription
0

No effect.
1

Disables the Receive Overrun Interrupt.

Bit 8 – CP0: Compare 0 Interrupt Disable

Compare 0 Interrupt Disable

ValueDescription
0

No effect.
1

Disables the Compare 0 Interrupt.

Bit 9 – CP1: Compare 1 Interrupt Disable

Compare 1 Interrupt Disable

ValueDescription
0

No effect.
1

Disables the Compare 1 Interrupt.

Bit 10 – TXSYN: Tx Sync Interrupt Enable

Tx Sync Interrupt Enable

ValueDescription
0

No effect.
1

Disables the Tx Sync Interrupt.

Bit 11 – RXSYN: Rx Sync Interrupt Enable

Rx Sync Interrupt Enable

ValueDescription
0

No effect.
1

Disables the Rx Sync Interrupt.