I2SC_MR

I2SC Mode Register

The I2SC_MR must be written when the I2SC is stopped. The proper sequence is to write to I2SC_MR, then write to I2SC_CR to enable the I2SC or to disable the I2SC before writing a new value to I2SC_MR.

  0x04 32 Read/Write 0x00000000  
Parent topic: Register Summary

I2SC Mode Register

Bit  31 30 29 28 27 26 25 24  
  IWS IMCKMODE IMCKFS[5:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
      IMCKDIV[5:0]  
Access      R/W R/W R/W R/W R/W R/W  
Reset      0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
    TXSAME TXDMA TXMONO   RXLOOP RXDMA RXMONO  
Access    R/W R/W R/W   R/W R/W R/W  
Reset    0 0 0   0 0 0  
Bit  7 6 5 4 3 2 1 0  
        DATALENGTH[2:0]   MODE  
Access        R/W R/W R/W   R/W  
Reset        0 0 0   0  

Bit 0 – MODE: Inter-IC Sound Controller Mode

Inter-IC Sound Controller Mode

ValueNameDescription
0 SLAVE

I2SC_CK and I2SC_WS pin inputs used as bit clock and word select/frame synchronization.
1 MASTER

Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SC_CK and I2SC_WS pins. Peripheral clock or GCLK is output as master clock on I2SC_MCK if I2SC_MR.IMCKMODE is set.

Bits 4:2 – DATALENGTH[2:0]: Data Word Length

Data Word Length

ValueNameDescription
0 32_BITS

Data length is set to 32 bits.
1 24_BITS

Data length is set to 24 bits.
2 20_BITS

Data length is set to 20 bits.
3 18_BITS

Data length is set to 18 bits.
4 16_BITS

Data length is set to 16 bits.
5 16_BITS_COMPACT

Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word.
6 8_BITS

Data length is set to 8 bits.
7 8_BITS_COMPACT

Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word.

Bit 9 – RXDMA: Single or Multiple DMA Controller Channels for Receiver

Single or Multiple DMA Controller Channels for Receiver

ValueDescription
0

The receiver uses only one DMA Controller channel for all audio channels.
1

The receiver uses one DMA Controller channel per audio channel.

Bit 8 – RXMONO: Receive Mono

Receive Mono

ValueDescription
0

Stereo
1

Mono, with left audio samples duplicated to right audio channel by the I2SC.

Bit 10 – RXLOOP: Loopback Test Mode

Loopback Test Mode

ValueDescription
0

Normal mode
1

I2SC_DO output of I2SC is internally connected to I2SC_DI input.

Bit 12 – TXMONO: Transmit Mono

Transmit Mono

ValueDescription
0

Stereo
1

Mono, with left audio samples duplicated to right audio channel by the I2SC.

Bit 13 – TXDMA: Single or Multiple DMA Controller Channels for TransmitterDMA Controller Channels for Transmitter

Single or Multiple DMA Controller Channels for TransmitterDMA Controller Channels for Transmitter

ValueDescription
0

The transmitter uses only one DMA Controller channel for all audio channels.
1

The transmitter uses one DMA Controller channel per audio channel.

Bit 14 – TXSAME: Transmit Data when Underrun

Transmit Data when Underrun

ValueDescription
0

Zero sample transmitted when underrun.
1

Previous sample transmitted when underrun

Bits 21:16 – IMCKDIV[5:0]: Selected Clock to I2SC Master Clock Ratio

Selected Clock to I2SC Master Clock Ratio

I2SC_MCK Master clock output frequency is Selected Clock divided by (IMCKDIV + 1). Refer to the IMCKFS field description.

Notes:
  1. 1.This field is write-only. Always read as ‘0’.
  2. 2.Do not write a ‘0’ to this field.

Bits 29:24 – IMCKFS[5:0]: Master Clock to fs Ratio

Master Clock to f

s Ratio

Master clock frequency is [2 x 16 × (IMCKFS + 1)] / (IMCKDIV + 1) times the sample rate, i.e., I2SC_WS frequency.

ValueNameDescription
0 M2SF32

Sample frequency ratio set to 32
1 M2SF64

Sample frequency ratio set to 64
2 M2SF96

Sample frequency ratio set to 96
3 M2SF128

Sample frequency ratio set to 128
5 M2SF192

Sample frequency ratio set to 192
7 M2SF256

Sample frequency ratio set to 256
11 M2SF384

Sample frequency ratio set to 384
15 M2SF512

Sample frequency ratio set to 512
23 M2SF768

Sample frequency ratio set to 768
31 M2SF1024

Sample frequency ratio set to 1024
47 M2SF1536

Sample frequency ratio set to 1536
63 M2SF2048

Sample frequency ratio set to 2048

Bit 30 – IMCKMODE: Master Clock Mode

Master Clock Mode

Warning: If I2SC_MCK frequency is the same as I2SC_CK, IMCKMODE must be cleared. Refer to section Serial Clock and Word Select Generation and table Slot Length.
ValueDescription
0

No master clock generated (Selected Clock drives I2SC_CK output).
1

Master clock generated (internally generated clock is used as I2SC_MCK output).

Bit 31 – IWS: I2SC_WS Slot Width

I2S

C_WS Slot Width

Refer to table Slot Length (I2S format).

ValueDescription
0

I2SC_WS slot is 32 bits wide for DATALENGTH = 18/20/24 bits.
1

I2SC_WS slot is 24 bits wide for DATALENGTH = 18/20/24 bits.