SSC_RHR

SSC Receive Holding Register

  0x20 32 Read-only 0x00000000  

SSC Receive Holding Register

Bit  31 30 29 28 27 26 25 24  
  RDAT[31:24]  
Access  R R R R R R R R  
Reset  0 0 0 0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
  RDAT[23:16]  
Access  R R R R R R R R  
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  RDAT[15:8]  
Access  R R R R R R R R  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  RDAT[7:0]  
Access  R R R R R R R R  
Reset  0 0 0 0 0 0 0 0  

Bits 31:0 – RDAT[31:0]: Receive Data

Receive Data

Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR.