TWIHS_SMR

TWIHS Slave Mode Register

  0x08 32 Read/Write 0x00000000  

TWIHS Slave Mode Register

Bit  31 30 29 28 27 26 25 24  
  DATAMEN SADR3EN SADR2EN SADR1EN          
Access  R/W R/W R/W R/W          
Reset  0 0 0 0          
Bit  23 22 21 20 19 18 17 16  
    SADR[6:0]  
Access    R/W R/W R/W R/W R/W R/W R/W  
Reset    0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
    MASK[6:0]  
Access    R/W R/W R/W R/W R/W R/W R/W  
Reset    0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
    SCLWSDIS              
Access    R/W              
Reset    0              

Bit 6 – SCLWSDIS: Clock Wait State Disable

Clock Wait State Disable

ValueDescription
0

No effect.

1

Clock stretching disabled in Slave mode, OVRE and UNRE indicate an overrun/underrun.

Bits 14:8 – MASK[6:0]: Slave Address Mask

Slave Address Mask

A mask can be applied on the slave device address in Slave mode in order to allow multiple address answer. For each bit of the MASK field set to 1, the corresponding SADR bit is masked.

If the MASK field value is 0, no mask is applied to the SADR field.

Bits 22:16 – SADR[6:0]: Slave Address

Slave Address

The slave device address is used in Slave mode in order to be accessed by master devices in Read or Write mode.

SADR must be programmed before enabling the Slave mode or after a general call. Writes at other times have no effect.

Bit 28 – SADR1EN: Slave Address 1 Enable

Slave Address 1 Enable

ValueDescription
0

Slave address 1 matching is disabled.

1

Slave address 1 matching is enabled.

Bit 29 – SADR2EN: Slave Address 2 Enable

Slave Address 2 Enable

ValueDescription
0

Slave address 2 matching is disabled.

1

Slave address 2 matching is enabled.

Bit 30 – SADR3EN: Slave Address 3 Enable

Slave Address 3 Enable

ValueDescription
0

Slave address 3 matching is disabled.

1

Slave address 3 matching is enabled.

Bit 31 – DATAMEN: Data Matching Enable

Data Matching Enable

ValueDescription
0

Data matching on first received data is disabled.

1

Data matching on first received data is enabled.