TWIHS_CWGR

TWIHS Clock Waveform Generator Register

This register can only be written if the WPEN bit is cleared in the TWIHS Write Protection Mode Register.

TWIHS_CWGR is used in Master mode only.

  0x10 32 Read/Write 0x00000000  
Parent topic: Register Summary

TWIHS Clock Waveform Generator Register

Bit  31 30 29 28 27 26 25 24  
      HOLD[5:0]  
Access      R/W R/W R/W R/W R/W R/W  
Reset      0 0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
            CKDIV[2:0]  
Access            R/W R/W R/W  
Reset            0 0 0  
Bit  15 14 13 12 11 10 9 8  
  CHDIV[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  CLDIV[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 7:0 – CLDIV[7:0]: Clock Low Divider

Clock Low Divider

The SCL low period is defined as follows:

tlow = ((CLDIV × 2CKDIV) + 3) × tperipheral clock

Bits 15:8 – CHDIV[7:0]: Clock High Divider

Clock High Divider

The SCL high period is defined as follows:

thigh = ((CHDIV × 2CKDIV) + 3) × tperipheral clock

Bits 18:16 – CKDIV[2:0]: Clock Divider

Clock Divider

The CKDIV is used to increase both SCL high and low periods.

Bits 29:24 – HOLD[5:0]: TWD Hold Time Versus TWCK Falling

TWD Hold Time Versus TWCK Falling

If High-speed mode is selected TWD is internally modified on the TWCK falling edge to meet the I2C specified maximum hold time, else if High-speed mode is not configured TWD is kept unchanged after TWCK falling edge for a period of (HOLD + 3) × tperipheral clock.