Notes:
1. 1.This bit requires the ON bit to be set.
2. 2.If cleared by software while a conversion is in progress, the results of the conversion up to this point will be transferred to ADRES and the state machine will be reset, but the ADIF interrupt flag bit will not be set; filter and threshold operations will not be performed.
Name:
Offset:
0x1D26
Reset:
Access:
 Bit7 6 5 4 3 2 1 0 ON CONT CS FM[1:0] IC GO AccessR/W R/W R/W R/W R/W R/W R/W/HC/HS Reset0 0 0 0 0 1 0

ValueDescription

## Bit 6 – CONT: ADC Continuous Operation Enable

ValueDescription
1 GO is retriggered upon completion of each conversion trigger until ADTIF is set (if SOI is set) or until GO is cleared (regardless of the value of SOI)
0 ADC is cleared upon completion of each conversion trigger

## Bit 4 – CS: ADC Clock Selection

ValueDescription
1 Clock supplied from ADCRC dedicated oscillator
0 Clock supplied by FOSC, divided according to the ADCLK register

## Bits 3:2 – FM[1:0]: ADC Results Format/Alignment Selection

ValueNameDescription
x1 IC = 0 ADRES and ADPREV data are right justified
x0 IC = 0 ADRES and ADPREV data are left justified, zero-filled
11 IC = 1 ADRES and ADPREV data are right justified, sign bit
10 IC = 1 ADRES and ADPREV data are left justified, sign bit, zero-filled
01 IC = 1 ADRES and ADPREV data are right justified, two’s complement
00 IC = 1 ADRES and ADPREV data are left justified, two’s complement, zero-filled