CLKRCLK

CLKRCLK

Clock Reference Clock Selection Register

Name:: CLKRCLK
Offset:: 0x0297
Reset:
Access:

Bit7	6	5	4	3	2	1	0
				CLK[3:0]
Access				R/W	R/W	R/W	R/W
Reset				0	0	0	0

Bits 3:0 – CLK[3:0]: CLKR Clock Selection

CLKR Clock Selection

Table 1. Clock Reference Module Clock Sources
CLK	Clock Source
`1111-1100`	Reserved
`1011`	CLC4_OUT
`1010`	CLC3_OUT
`1001`	CLC2_OUT
`1000`	CLC1_OUT
`0111`	NCO1_OUT
`0110`	EXTOSC
`0101`	SOSC
`0100`	MFINTOSC (32 kHz)
`0011`	MFINTOSC (500 kHz)
`0010`	LFINTOSC
`0001`	HFINTOSC
`0000`	F_OSC