NOSC and NDIV Bits

The New Oscillator Source Request (NOSC) and the New Divider Selection Request (NDIV) bits are used to select the system clock source and clock frequency divider that will be used by the CPU and peripherals (see the tables below).

When new values are written into NOSC and/or NDIV, the current oscillator selection will continue to operate as the system clock while waiting for the new source to indicate that it is ready. Writes to NDIV without changing the clock source (e.g., changing the HFINTOSC frequency from 1 MHz to 2 MHz) are handled in the same manner as a clock switch.

When the new oscillator selection is ready, the New Oscillator is Ready (NOSCR) bit and the Clock Switch Interrupt Flag (CSWIF) are set by module hardware. If the Clock Switch Interrupt Enable (CSWIE) bit is set (CSWIE = 1), an interrupt will be generated when CSWIF is set. Additionally, the Oscillator Ready (ORDY) bit can be polled to determine that the clock switch has completed and the new oscillator source has replaced the old source as the system clock.
Important: The CSWIF interrupt does not wake the device from Sleep.
Table 1. NOSC/COSC Clock Source Selection Table
NOSC / COSC Clock Source
111 EXTOSC(1)
110 HFINTOSC(2)
101 LFINTOSC
100 SOSC
011 Reserved
010 EXTOSC + 4xPLL(3)
001 Reserved
000 Reserved
Notes:
1. 1.EXTOSC is configured via the FEXTOSC Configuration bits.
2. 2.HFINTOSC frequency is determined by the FRQ bits.
3. 3.EXTOSC must meet the PLL specifications (see the data sheet Electrical Specifications).
Table 2. NDIV/CDIV Clock Divider Selection Table
NDIV / CDIV Clock Divider
1111-1010 Reserved
1001 512
1000 256
0111 128
0110 64
0101 32
0100 16
0011 8
0010 4
0001 2
0000 1