I2C Host Mode

Host mode is enabled by configuring the appropriate SSPM bits and setting the SSPEN bit. In Host mode, the SDA and SCL pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low.

Host mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is set, or the bus is Idle.

In Firmware Controlled Host mode, user code conducts all I2C bus operations based on Start and Stop condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user software directly manipulating the SDA and SCL lines.

The following events will cause the MSSP Interrupt Flag (SSPxIF) bit to be set (MSSP interrupt, if enabled):

  1. 1.The MSSP module, when configured in I2C Host mode, does not allow queuing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, SSPxBUF will not be written to and the Write Collision Detect (WCOL) bit will be set, indicating that a write to SSPxBUF did not occur.
  2. 2.Host mode suspends Start/Stop detection when sending the Start/Stop condition by means of the SEN/PEN control bits. The SSPxIF bit is set at the end of the Start/Stop generation when hardware clears the control bit.