ADC Acquisition Requirements

For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The maximum recommended impedance for analog sources is 10 kΩ. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an ADC acquisition time must be completed before the conversion can be started. To calculate the minimum acquisition time, Figure 1 may be used. This equation assumes an error of 1/2 LSb. The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution.

Figure 1. Acquisition Time Example

Assumptions: Temperature = 50°C; External impedance = 10 kΩ; VDD = 5.0V

TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

TACQ=TAMP+TC+TCOFF

TACQ=2μs+TC+[(Temperature25°C)(0.05μs/°C)]

The value for TC can be approximated with the following equations:

VAPPLIED(11(2n+1)1)=VCHOLD ; [1] VCHOLD charged to within ½ LSb

VAPPLIED(1eTCRC)=VCHOLD ; [2] VCHOLD charge response to VAPPLIED

VAPPLIED(1eTCRC)=VAPPLIED(11(2n+1)1) ; Combining [1] and [2]

Note: Where n = ADC resolution in bits

Solving for TC:

TC=CHOLD(RIC+RSS+RS)ln(1/8191)

TC=28pF(1kΩ+7kΩ+10kΩ)ln(0.0001221)

TC=4.54μs

Therefore:

TACQ=2μs+4.54μs+[(50°C25°C)(0.05μs/°C)]

TACQ=7.79μs

Important:
Figure 2. Analog Input Model
Figure 3. ADC Transfer Function