SSPxCON1

MSSP Control Register 1
Notes:
  1. 1.In Host mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register.
  2. 2.When enabled, these pins must be properly configured as inputs or outputs.
  3. 3.SSPxADD = 0 is not supported.
  4. 4.Bit combinations not specifically listed here are either reserved or implemented in I2C mode only.
Name:
SSPxCON1
Offset:
0x0790,0x079A
Reset:
Access:
Bit76543210
WCOLSSPOVSSPENCKPSSPM[3:0]
AccessR/W/HSR/W/HSR/WR/WR/WR/WR/WR/W
Reset00000000

Bit 7 – WCOL

Write Collision Detect bit
ValueNameDescription
x Host or Client receive This bit is not used
1 SPI or I2C Host or Client transmit The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 SPI or I2C Host or Client transmit No collision

Bit 6 – SSPOV

Receive Overflow Indicator bit(1)
ValueNameDescription
x SPI Host or I2C Host transmit This bit is not used
1 SPI Client A byte is received while the SSPxBUF register is still holding the previous byte. Data contained in the shift register will be discarded. The user must read SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software).
1 I2C Receive A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in software)
0 SPI Client or I2C Receive No overflow

Bit 5 – SSPEN

Host Synchronous Serial Port Enable bit.(2)
ValueDescription
1 Enables the serial port
0 Disables serial port and configures these pins as I/O PORT pins

Bit 4 – CKP

SCK Release Control bit
ValueNameDescription
x I2C Host This bit is not used
1 SPI Idle state for the clock is a high level
0 SPI Idle state for the clock is a low level
1 I2C Client Releases clock
0 I2C Client Holds clock low (clock stretch), used to ensure data setup time

Bits 3:0 – SSPM[3:0]

Host Synchronous Serial Port Mode Select bits(4)
ValueDescription
1111 I2C Client mode: 10-bit address with Start and Stop bit interrupts enabled
1110 I2C Client mode: 7-bit address with Start and Stop bit interrupts enabled
1101 Reserved - do not use
1100 Reserved - do not use
1011 I2C Firmware Controlled Host mode (client Idle)
1010 SPI Host mode: Clock = FOSC/(4*(SSPxADD+1)). SSPxADD must be greater than 0.(3)
1001 Reserved - do not use
1000 I2C Host mode: Clock = FOSC/(4 * (SSPxADD + 1))
0111

I2C Client mode: 10-bit address

0110 I2C Client mode: 7-bit address
0101 SPI Client mode: Clock = SCKx pin. SSx pin control is disabled
0100 SPI Client mode: Clock = SCKx pin. SSx pin control is enabled
0011 SPI Host mode: Clock = TMR2 output/2
0010 SPI Host mode: Clock = FOSC/64
0001 SPI Host mode: Clock = FOSC/16
0000 SPI Host mode: Clock = FOSC/4