PIR2

Peripheral Interrupt Request Register 2
Note: Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.
Name:
PIR2
Offset:
0x008E
Reset:
Access:
Bit76543210
CCP2IFCCP1IFTMR4IFTMR2IFTMR3GIFTMR3IF
AccessR/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HS
Reset000000

Bit 6 – CCP2IF: CCP2 Interrupt Flag

CCP2 Interrupt Flag

Value CCP Mode
Capture Compare PWM
1 Capture occurred (must be cleared in software) Compare match occurred (must be cleared in software) Output trailing edge occurred (must be cleared in software)
0 Capture did not occur Compare match did not occur Output trailing edge did not occur

Bit 5 – CCP1IF: CCP1 Interrupt Flag

CCP1 Interrupt Flag

Value CCP Mode
Capture Compare PWM
1 Capture occurred (must be cleared in software) Compare match occurred (must be cleared in software) Output trailing edge occurred (must be cleared in software)
0 Capture did not occur Compare match did not occur Output trailing edge did not occur

Bit 3 – TMR4IF: TMR4 Interrupt Flag

TMR4 Interrupt Flag

ValueDescription
1 TMR4 interrupt has occurred (must be cleared in software)
0 TMR4 interrupt event has not occurred

Bit 2 – TMR2IF: TMR2 Interrupt Flag

TMR2 Interrupt Flag

ValueDescription
1 TMR2 interrupt has occurred (must be cleared in software)
0 TMR2 interrupt event has not occurred

Bit 1 – TMR3GIF: TMR3 Gate Interrupt Flag

TMR3 Gate Interrupt Flag

ValueDescription
1 The TMR3 Gate has gone inactive (must be cleared in software)
0 TMR3 Gate is active

Bit 0 – TMR3IF: TMR3 Interrupt Flag

TMR3 Interrupt Flag

ValueDescription
1 TMR3 interrupt has occurred (must be cleared in software)
0 TMR3 interrupt event has not occurred