PIR3

Peripheral Interrupt Request Register 3
Note: Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.
Name:
PIR3
Offset:
0x008F
Reset:
Access:
Bit76543210
PWM2IFPWM2PIFPWM1IFPWM1PIF
AccessR/W/HSR/W/HSR/W/HSR/W/HS
Reset0000

Bit 3 – PWM2IF: PWM2 Parameter Interrupt Flag

PWM2 Parameter Interrupt Flag

ValueDescription
1 PWM2 Parameter interrupt has occurred (must be cleared in software)
0 PWM2 Parameter interrupt event has not occurred

Bit 2 – PWM2PIF: PWM2 Period Interrupt Flag

PWM2 Period Interrupt Flag

ValueDescription
1 PWM2 Period interrupt has occurred (must be cleared in software)
0 PWM2 Period interrupt event has not occurred

Bit 1 – PWM1IF: PWM1 Parameter Interrupt Flag

PWM1 Parameter Interrupt Flag

ValueDescription
1 PWM1 Parameter interrupt has occurred (must be cleared in software)
0 PWM1 Parameter interrupt event has not occurred

Bit 0 – PWM1PIF: PWM1 Period Interrupt Flag

PWM1 Period Interrupt Flag

ValueDescription
1 PWM1 Period interrupt has occurred (must be cleared in software)
0 PWM1 Period interrupt event has not occurred