RCxSTA

Receive Status and Control Register
Name:
RCxSTA
Offset:
0x0710,0x071A
Reset:
Access:
Bit76543210
SPENRX9SRENCRENADDENFERROERRRX9D
AccessR/WR/WR/W/HCR/WR/WRR/HCR/HC
Reset00000000

Bit 7 – SPEN: Serial Port Enable

Serial Port Enable

ValueDescription
1 Serial port enabled
0 Serial port disabled (held in Reset)

Bit 6 – RX9: 9-Bit Receive Enable

9-Bit Receive Enable

ValueDescription
1 Selects 9-bit reception
0 Selects 8-bit reception

Bit 5 – SREN: Single Receive Enable

Single Receive Enable

Controls reception. This bit is cleared by hardware when reception is complete

ValueNameDescription
1 SYNC = 1 AND CSRC = 1 Start single receive
0 SYNC = 1 AND CSRC = 1 Single receive is complete
X SYNC = 0 OR CSRC = 0 Don’t care

Bit 4 – CREN: Continuous Receive Enable

Continuous Receive Enable

ValueNameDescription
1 SYNC = 1 Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 SYNC = 1 Disables continuous receive
1 SYNC = 0 Enables receiver
0 SYNC = 0 Disables receiver

Bit 3 – ADDEN: Address Detect Enable

Address Detect Enable

ValueNameDescription
1 SYNC = 0 AND RX9 = 1 The receive buffer is loaded and the interrupt occurs only when the ninth received bit is set
0 SYNC = 0 AND RX9 = 1 All bytes are received and interrupt always occurs. Ninth bit can be used as parity bit
X RX9 = 0 OR SYNC = 1 Don't care

Bit 2 – FERR: Framing Error

Framing Error

ValueDescription
1 Unread byte in RCxREG has a framing error
0 Unread byte in RCxREG does not have a framing error

Bit 1 – OERR: Overrun Error

Overrun Error

ValueDescription
1 Overrun error (can be cleared by clearing either SPEN or CREN bit)
0 No overrun error

Bit 0 – RX9D: Ninth bit of Received Data

Ninth bit of Received Data

This can be address/data bit or a parity bit which is determined by user firmware.