Name:
Offset:
0x049E
Reset:
Access:
 Bit7 6 5 4 3 2 1 0 MPWM2LD MPWM1LD Access R/W R/W Reset 0 0

## Bits 0, 1 – MPWMxLD: Mirror copy of PWMxLD bitDo not remove the word “bit” here as it refers to the bit in another register

Mirror copy of PWMxLD bit

Mirror copies of all PWMxLD bits can be set simultaneously to synchronize the load event across all PWMs
ValueDescription
1 PWMx parameter and period values will be transferred to their buffer registers at the next period Reset event
0 There are no PWMx period and parameter value transfers pending