PIR1

Peripheral Interrupt Request Register 1
Note: Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.
Name:
PIR1
Offset:
0x008D
Reset:
Access:
Bit76543210
TMR1GIFTMR1IFOSFIFCSWIFACTIFSCANIFCRCIFNVMIF
AccessR/W/HSR/W/HSRRR/W/HSR/W/HSR/W/HSR/W/HS
Reset00000000

Bit 7 – TMR1GIF: TMR1 Gate Interrupt Flag

TMR1 Gate Interrupt Flag

ValueDescription
1 The TMR1 Gate has gone inactive (must be cleared in software)
0 TMR1 Gate is active

Bit 6 – TMR1IF: TMR1 Interrupt Flag

TMR1 Interrupt Flag

ValueDescription
1 TMR1 interrupt has occurred (must be cleared in software)
0 TMR1 interrupt event has not occurred

Bit 5 – OSFIF: Oscillator Failure Interrupt Flag

Oscillator Failure Interrupt Flag

ValueDescription
1 An oscillator failure event has been detected (must be cleared in software)
0 An oscillator failure event has not been detected

Bit 4 – CSWIF: Clock Switch Interrupt Flag

Clock Switch Interrupt Flag

ValueDescription
1 A Clock Switch interrupt has occurred (must be cleared in software)
0 A Clock Switch interrupt event has not occurred

Bit 3 – ACTIF: Active Clock Tuning Interrupt Flag

Active Clock Tuning Interrupt Flag

ValueDescription
1 Active Clock Tuning interrupt occurred (must be cleared in software)
0 Active Clock Tuning interrupt event has not occurred

Bit 2 – SCANIF: Memory Scanner Interrupt Flag

Memory Scanner Interrupt Flag

ValueDescription
1 Memory Scanner interrupt has occurred (must be cleared in software)
0 Memory Scanner interrupt event has not occurred

Bit 1 – CRCIF: CRC Interrupt Flag

CRC Interrupt Flag

ValueDescription
1 CRC interrupt has occurred (must be cleared in software)
0 CRC interrupt event has not occurred

Bit 0 – NVMIF: Nonvolatile Memory (NVM) Interrupt Flag

Nonvolatile Memory (NVM) Interrupt Flag

ValueDescription
1 The requested NVM operation has completed (must be cleared in software)
0 NVM interrupt event has not occurred