Register Summary - CLC Control

Offset Name Bit Pos. 7 6 5 4 3 2 1 0

0x00

...

0x068B

Reserved                  
0x068C CLCnCON 7:0 EN   OUT INTP INTN MODE[2:0]
0x068D CLCnPOL 7:0 POL       G4POL G3POL G2POL G1POL
0x068E CLCnSEL0 7:0   D1S[6:0]
0x068F CLCnSEL1 7:0   D2S[6:0]
0x0690 CLCnSEL2 7:0   D3S[6:0]
0x0691 CLCnSEL3 7:0   D4S[6:0]
0x0692 CLCnGLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N
0x0693 CLCnGLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N
0x0694 CLCnGLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N
0x0695 CLCnGLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N
0x0696 CLCSELECT 7:0         SLCT[3:0]
0x0697 CLCDATA 7:0         CLC4OUT CLC3OUT CLC2OUT CLC1OUT