Ensure that the placement for the DDR3 memories looks like L (shape), where, memories are at the bottom of the L and controllers are on the top of the L. This gives enough space to route the DQ signals with less number of layers.

Note: This is not mandatory to follow the suggested placement. However, the placement also depends on the board constraints. The maximum trace length of any signal in the placement must not be more than 7 inches.
Figure 1. DDR3 Memories

The termination resistors are not required for the DQ and DQS signals as these signals have on chip ODTs. The termination resistors are placed at the end of the address, command, control, and clock signals as these signals use fly-by topology. VTT plane/island is thick enough to handle the current required by termination resistors; at least 150 mil trace is required. The sense pin of VTT regulator must be connected at the center of the VTT island.