The AHB-APB bridge is an AHB slave, providing an interface between the high-speed
AHB domain and the low-power APB domain. It is used to provide access to the
programmable control registers of peripherals (see Product Mapping).
AHB-APB bridge is based on AMBA APB Protocol Specification V2.0 (ref. as APB4)
including:
- Wait state support
- Error reporting
- Transaction protection
- Sparse data transfer (byte, half-word and word)
Additional enhancements:
- Address and data cycles merged
into a single cycle
- Sparse data transfer also apply
to read access
to operate the AHB-APB bridge, the clock (CLK_HPBx_AHB) must be enabled. See
PM
– Power Manager for details.
Figure 1. APB Write Access.
Figure 2. APB Read Access.