The high-speed bus is implemented as a Bus Matrix. All high-speed bus addresses are fixed, and they are never remapped in any way, even during boot. The 32-bit physical address space is mapped as given in the below table.
Memory | Start Address | Size (Kbytes) | ||||
---|---|---|---|---|---|---|
SAMD20x18 | SAMD20x17 | SAMD20x16 | SAMD20x15 | SAMD20x14 | ||
Internal Flash | 0x00000000 | 256 | 128 | 64 | 32 | 16 |
Internal SRAM | 0x20000000 | 32 | 16 | 8 | 4 | 2 |
Peripheral Bridge A | 0x40000000 | 64 | 64 | 64 | 64 | 64 |
Peripheral Bridge B | 0x41000000 | 64 | 64 | 64 | 64 | 64 |
Peripheral Bridge C | 0x42000000 | 64 | 64 | 64 | 64 | 64 |
Device | Flash Size | Number of Pages | Page Size | Row Size |
---|---|---|---|---|
SAMD20x18 | 256 Kbytes | 4096 | 64 bytes | 4 pages = 256 bytes |
SAMD20x17 | 128 Kbytes | 2048 | 64 bytes | 4 pages = 256 bytes |
SAMD20x16 | 64 Kbytes | 1024 | 64 bytes | 4 pages = 256 bytes |
SAMD20x15 | 32 Kbytes | 512 | 64 bytes | 4 pages = 256 bytes |
SAMD20x14 | 16 Kbytes | 256 | 64 bytes | 4 pages = 256 bytes |