Programming the Flash or RAM memories is only possible when the
device is not protected by the NVMCTRL security bit. The programming procedure is as
follows:
- 1.At power up,
RESET is driven low by a debugger. The on-chip
regulator holds the system in a POR state until the input supply is above the
POR threshold (refer to Powe-On Reset (POR) characteristics). The system
continues to be held in this static state until the internally regulated
supplies have reached a safe operating state.
- 2.The PM
starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash
Clock and any Bus Clocks that do not have clock gate control). Internal resets
are maintained due to the external reset.
- 3.The debugger
maintains a low level on SWCLK. RESET is released,
resulting in a debugger Cold-Plugging procedure.
- 4.The debugger
generates a clock signal on the SWCLK pin, the Debug Access Port (DAP) receives
a clock.
- 5.The CPU
remains in Reset due to the Cold-Plugging procedure; meanwhile, the rest of the
system is released.
- 6.A Chip-Erase
is issued to ensure that the Flash is fully erased prior to programming.
- 7.Programming
is available through the AHB-AP.
- 8.After the
operation is completed, the chip can be restarted either by asserting
RESET or toggling power. Make sure
that the SWCLK pin is high when releasing RESET to
prevent extending the CPU reset.