VDDCORE and VDDCPU Dynamic Power

The dynamic power consumed by the logic circuits in the VDDCPU and VDDCORE domains depends on the application use case, i.e., the circuit activity (enabled circuits and their frequency) and the supply voltage at which they are operated. It is commonly known that the dynamic power consumption of a digital circuit has:

• a linear dependence to its operating frequency, and
• a quadratic dependence to its supply voltage.

For example, operating a CPU circuit at 400 MHz instead of 800 MHz divides by two its dynamic power consumption. Furthermore, if the reduced operating frequency allows a 5% VDD reduction, then an additional 10% power is saved. Adjusting at runtime the frequency and the voltage of a digital circuit to optimize its power consumption is a technique known as Dynamic Voltage and Frequency Scaling (DVFS).

SAMA7G5 devices are designed to support DVFS techniques on their VDDCPU supply:

• The SAMA7G5 Series data sheet defines several voltage ranges for VDDCPUs that have corresponding CPU frequency ranges.
• The clock control of the CPU island, in the Power Management Controller (PMC), is designed to scale the processor frequency upon request at runtime.

For example, for the experiments covered in this application note, the following Power-Performance states (P states) are defined in the Microchip Linux Device Tree (DT) for the SAMA7G54 processor. These are the operating points the kernel can choose to operate on:

• f_CPU = 90 MHz / VDDCPU = 1.05V
• f_CPU = 250 MHz / VDDCPU = 1.05V
• f_CPU = 600 MHz / VDDCPU = 1.10V
• f_CPU = 800 MHz / VDDCPU = 1.15V
• f_CPU = 1 GHz / VDDCPU = 1.25V

The SAMA7G5 logic circuits powered by VDDCORE cannot have their frequency changed dynamically. To optimize the dynamic power consumption in this power domain, the following actions are possible:

• The generic and peripheral clocks feeding unused peripherals must be disabled. This can be done at runtime to save power when needed in the PMC.
• The frequency of the MCKx clocks can be set to 100 MHz instead of 200 MHz, for example. This limits the internal bandwidth of the interconnect but may be possible in some applications cases. Note that, unlike the CPU frequency, this is a static setting that cannot be changed dynamically at runtime.