VDDCORE and VDDCPU Dynamic Power

The dynamic power consumed by the logic circuits in the VDDCPU and VDDCORE domains depends on the application use case, i.e., the circuit activity (enabled circuits and their frequency) and the supply voltage at which they are operated. It is commonly known that the dynamic power consumption of a digital circuit has:

For example, operating a CPU circuit at 400 MHz instead of 800 MHz divides by two its dynamic power consumption. Furthermore, if the reduced operating frequency allows a 5% VDD reduction, then an additional 10% power is saved. Adjusting at runtime the frequency and the voltage of a digital circuit to optimize its power consumption is a technique known as Dynamic Voltage and Frequency Scaling (DVFS).

SAMA7G5 devices are designed to support DVFS techniques on their VDDCPU supply:

For example, for the experiments covered in this application note, the following Power-Performance states (P states) are defined in the Microchip Linux Device Tree (DT) for the SAMA7G54 processor. These are the operating points the kernel can choose to operate on:

The SAMA7G5 logic circuits powered by VDDCORE cannot have their frequency changed dynamically. To optimize the dynamic power consumption in this power domain, the following actions are possible: