The following steps should be followed when setting up the CLC:
- Disable CLC by clearing the EN bit.
- Select desired inputs using the CLCxSEL0 through CLCxSEL3 registers (See CLC Data Input Table).
- Clear any associated ANSEL bits.
- Set all TRIS bits associated with inputs.
- Enable the chosen inputs through the four gates using the CLCxGLS0 through CLCxGLS3 registers.
- Select the gate output polarities
with the GyPOL bits
- Select the desired logic function
with the MODE bits
- Select the desired polarity of the
logic output with the POL bit. (This step may be combined with the
previous gate output polarity step).
- If driving a device pin, set the desired pin PPS control register and also clear the
TRIS bit corresponding to that output.
- Configure the interrupts (optional). See CLC Interrupts
- Enable the CLC by setting the EN bit.