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High-Performance Digital Signal Controllers with High-Resolution PWM and CAN Flexible Data-Rate (CAN FD)
Operating Conditions
Core: dsPIC33CK CPU
Clock Management
Power Management
High-Resolution PWM with Fine Edge Placement
Timers/Output Compare/Input Capture
Advanced Analog Features
Communication Interfaces
Direct Memory Access (DMA)
Peripheral Features
Debugger Development Support
Safety Features
Functional Safety Support – ISO 26262/IEC 61508/IEC 60730
Qualification Support
dsPIC33CK1024MP710 Product Families
Pin Diagrams
Pin Diagrams (Continued)
Pin Diagrams (Continued)
Pin Diagrams (Continued)
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Referenced Sources
1 Device Overview
2 Guidelines for Getting Started with Digital Signal Controllers
2.1 Basic Connection Requirements
2.2 Decoupling Capacitors
2.3 Master Clear (MCLR) Pin
2.4 ICSP Pins
2.5 External Oscillator Pins
2.6 External Oscillator Layout Guidance
2.7 Oscillator Value Conditions on Device Start-up
2.8 Unused I/Os
2.9 Bulk Capacitors
2.10 Targeted Applications
3 CPU
3.1 Registers
3.2 Instruction Set
3.3 Data Space Addressing
3.4 Addressing Modes
3.5 CPU Control/Status Registers
3.6 Arithmetic Logic Unit (ALU)
3.7 DSP Engine
4 Memory Organization
4.1 Program Address Space
4.2 Data Address Space
4.3 BIST Overview
4.4 Memory Resources
5 Flash Program Memory
5.1 Table Instructions and Flash Programming
5.2 RTSP Operation
5.3 Error Correcting Code (ECC)
5.4 ECC Fault Injection
5.5 Flash OTP by ICSP™ Write Inhibit
5.6 Dual Partition Flash Configuration
5.7 NVM/ECC Control Registers
6 Resets
6.1 Reset Resources
7 Interrupt Controller
7.1 Interrupt Vector Table
7.2 Alternate Interrupt Vector Table
7.3 Reset Sequence
7.4 Interrupt Resources
7.5 Interrupt Control and Status Registers
7.6 Status/Control Registers
7.7 Status/Control Registers
8 I/O Ports
8.1 Parallel I/O (PIO) Ports
8.2 Configuring Analog and Digital Port Pins
8.3 Input Change Notification (ICN)
8.4 Peripheral Pin Select (PPS)
8.5 Considerations for Peripheral Pin Selection
8.6 Input Mapping
8.7 Virtual Connections
8.8 Output Mapping
8.9 Mapping Limitations
8.10 I/O Helpful Tips
8.11 I/O Ports Resources
8.12 Peripheral Pin Select Control Registers
9 Oscillator with High-Frequency PLL
9.1 Primary PLL
9.2 Auxiliary PLL
9.3 CPU Clocking
9.4 Primary Oscillator (POSC)
9.5 Internal Fast RC (FRC) Oscillator
9.6 Low-Power RC Oscillator
9.7 Backup Internal Fast RC (BFRC) Oscillator
9.8 Reference Clock Output
9.9 Oscillator Configuration
9.10 OSCCON Unlock Sequence
9.11 Oscillator Control Registers
10 Direct Memory Access (DMA) Controller
10.1 Summary of DMA Operations
10.2 Typical Setup
11 Controller Area Network Flexible Data-Rate (CAN FD) Modules
11.1 Features
11.2 CAN Control/Status Registers
12 High-Resolution PWM with Fine Edge Placement
12.1 Features
12.2 Architecture Overview
12.3 Lock and Write Restrictions
12.4 PWM4H/L Output on Peripheral Pin Select
12.5 PWM Control/Status Registers
12.6 Control Registers
13 High-Speed, 12-Bit Analog-to-Digital Converter
13.1 ADC Features Overview
13.2 Temperature Sensor
13.3 Analog-to-Digital Converter Resources
13.4 ADC Control Registers
14 High-Speed Analog Comparator with Slope Compensation DAC
14.1 Overview
14.2 Features Overview
14.3 DAC Control Registers
14.4 DAC Control Registers
15 Quadrature Encoder Interface (QEI)
15.1 QEI Control/Status Registers
16 Universal Asynchronous Receiver Transmitter (UART)
16.1 Architectural Overview
16.2 Character Frame
16.3 Data Buffers
16.4 Protocol Extensions
16.5 UART Control/Status Registers
17 Serial Peripheral Interface (SPI)
17.1 SPI Control/Status Registers
18 Inter-Integrated Circuit (I2C)
18.1 Communicating as a Host in a Single Host Environment
18.2 Setting Baud Rate When Operating as a Bus Host
18.3 Client Address Masking
18.4 SMBus Support
18.5 I2C Control/Status Registers
19 Parallel Master Port (PMP)
19.1 Parallel Master Port Control Registers
20 Single-Edge Nibble Transmission (SENT)
20.1 Transmit Mode
20.2 Receive Mode
20.3 SENT Control/Status Registers
21 Timer1
21.1 Timer1 Control Register
22 Capture/Compare/PWM/Timer Modules (SCCP)
22.1 Time Base Generator
22.2 General Purpose Timer
22.3 Output Compare Mode
22.4 Input Capture Mode
22.5 Auxiliary Output
22.6 SCCP Control/Status Registers
23 Configurable Logic Cell (CLC)
23.1 CLC Control Registers
24 Peripheral Trigger Generator (PTG)
24.1 Features
24.2 PTG Registers
24.3 PTG Step Commands
25 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator
25.1 CRC Control Registers
26 Current Bias Generator (CBG)
26.1 Current Bias Generator Control Registers
27 Operational Amplifier
27.1 Operational Amplifier Control Registers
28 Deadman Timer (DMT)
28.1 Deadman Timer Control/Status Registers
29 Power-Saving Features
29.1 Clock Frequency and Clock Switching
29.2 Instruction-Based Power-Saving Modes
29.3 Doze Mode
29.4 Peripheral Module Disable
29.5 Power-Saving Resources
29.6 Power-Saving Control Registers
30 Special Features
30.1 Configuration Bits
30.2 Configuration Registers
30.3 FBOOT Configuration Register
FBOOT Configuration Register
30.4 Device Calibration and Identification
30.5 User OTP Memory
30.6 On-Chip Voltage Regulators
30.7 Brown-out Reset (BOR)
30.8 Dual Watchdog Timer (WDT)
30.9 JTAG Interface
30.10 In-Circuit Debugger
30.11 Code Protection and CodeGuard™ Security
31 Instruction Set Summary
32 Development Support
33 Electrical Characteristics
33.1 DC Characteristics
33.2 AC Characteristics and Timing Parameters
34 High-Temperature Electrical Characteristics
34.1 DC Characteristics
35 Packaging Information
35.1 Package Marking Information
35.2 Package Marking Information (Continued)
35.3 Package Details
36 Revision History
Product Identification System
Microchip Information
Trademarks
Legal Notice
Microchip Devices Code Protection Feature

DS70005496D

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