I/O Banks

PolarFire SoC FPGA device has eight user I/O banks, whereas PolarFire FPGA device has five, six, or eight user I/O banks depending upon the device size.

The I/O banks on the north side of the device support only HSIO. Each I/O bank has dedicated I/O supplies and grounds. Each I/O within a given bank shares the same VDDI power supply and VREF reference voltage. Only compatible I/O standards can be assigned to a given I/O bank.

Each bank contains a bank power detector and a bank receiver reference voltage generator to create an internally generated reference voltage, VREF. Each bank also interfaces with a PVT controller to calibrate the I/O buffer output driver strengths and termination values (needed only for certain I/O standards). The PVT controller generates a set of codes to control the source driver and the sink driver, and also calibrates the HSIO output slew. Each I/O buffer has individual drive-strength programmability to multiply the PVT digital code value by a drive setting to create the desired drive, impedance, or termination settings. For more information, see I/O Analog (IOA) Buffer Programmable Features.

Figure 1 through Figure 5 show simplified floorplans for each device, including the bank locations. These figures also show the corner block and transceiver block. The corner block includes CCCs, two PLLs, and two DLLs each, providing flexible clock management and synthesis for the FPGA fabric, external system, and I/Os. All banks are not available in all devices, see I/O Lanes in Each Bank for more information. For more information about CCC and transceivers, see PolarFire FPGA and PolarFire SoC FPGA Clocking Resources User Guide and PolarFire FPGA and PolarFire SoC FPGA Transceiver User Guide.

Figure 1. PolarFire FPGA MPF300T, MPF300XT, and MPF500T Device I/O Banks
Figure 2. PolarFire FPGA MPF200T Device I/O Banks
Figure 3. PolarFire FPGA MPF100T Device I/O Banks
Figure 4. PolarFire SoC FPGA MPFS250–FCG1152 I/O Banks
Figure 5. PolarFire SoC FPGA MPFS250–FCVG484 I/O Banks