LVDS

GPIO and HSIO banks can receive LVDS input signals. For GPIO, these inputs have an internal 100 Ω differential termination resistor that can be enabled by the Libero SoC software. HSIO does not have this internal resistor capability. HSIO requires a 100 Ω resistor across the P and N pair of the LVDS inputs. This requires careful PCB layout to provide this termination close to the device pins.

HSIO banks only support LVDS18 inputs. LVDS18 outputs are not available. Only emulated LVDS-like outputs with lower performance are available in HSIO banks. True LVDS outputs are natively available in GPIO banks. Use either VDDI = 2.5 V or 3.3 V (LVDS25 or LVDS33) or LVDS18G with VDDI = 1.8 V and VDDAUX = 2.5 V. See LVDS in GPIO Banks with VDDI = 1.8 V for more information about GPIO LVDS18G inputs and outputs. For more information about DC specification, see respective PolarFire FPGA Datasheet or PolarFire SoC Advance Datasheet. LVDS outputs are not available in HSIO banks.