Power-Up and Initialization

The following table lists the I/O states during power-up and initialization modes.

Table 1. I/O States during Power-Up and Initialization
Device State I/O State
Power-up start/powering up Tri-state

I/O buffers are disabled.

Output drivers are disabled (tri-stated).

Receivers are disabled (input signals are not passed to the FPGA fabric).

All terminations, PCI clamp diodes, and weak pull-up/down modes are off.

All I/O bank power detectors and PVT controllers are disabled.

User mode The buffer is programmed based on Libero SoC I/O settings.

Data and output enable signals are based on user settings.

For more information about I/O states, see PolarFire FPGA and PolarFire SoC FPGA Programming User Guide.

For more information about I/O settings for unused I/O pins, see PPAT spreadsheets.