Clock to Data Margin Training

Margin control training of the IOD interface maximizes the valid window by continuously monitoring and controlling the delays using the dynamic delay control signals. This operation is used to compensate for the PVT variations with high-speed source synchronous interfaces. The main reason for this capability is to optimize the signal integrity of the high-speed IOD interfaces by maintaining margin between the data and clock paths. Interface training is controlled and monitored by FPGA hosted IP (that is, training IP or TIP).

Figure 1. Clock to Data Training Data Path

The TIP uses the dynamic delay control pins of the dynamic RX_DDRX interface components to optimize the receive relationship between the clock and data. Status flags are used to dynamically monitor the relationship of the clock and data at the IREG and uses dynamic controls to adjust the delay chain by adding or removing delay elements in the data path. The delay setting is adjusted to move the data edges earlier or later relative to the clock edges. This feature monitors the relation of the data edges to both the positive and negative clock edges.

FPGA fabric hosted logic is used to control and monitor IOD signals to perform adaptive tuning functions on a bit- or word-wide basis. Bit alignment is the alignment of the data to be 90 degrees centered from the clock edges. This is a physical layer function that is independent of the data or protocol being used. This step requires the transmitter to send data (with transitions) and has a static alignment with the forwarded clock.

RX_DDRX_DYN macro provides controls to add or remove delay from the data path relative to the clock path. The RX_DDRX_DYN also provides flags using the eye monitor which can identify when the data and clock are too close together and side of the clock in which the violation occurs. Using these controls and flags, bit alignment can be performed by only looking at the physical layer.

Word Alignment is the alignment of the fabric presented word to a specific pattern. The RX_DDRX_DYN provides IO gearing and supports both a 4-bit and 8-bit fabric width. Byte alignment is data pattern dependent and would require a training pattern. When the transmitter sends the training pattern, a pattern detector in the FPGA fabric would use the Lx_BITSLIP port on the RX_DDRX_DYN to rotate the fabric word till the training pattern is found.

The signal, “DELAY_LINE_LOAD” asynchronously reloads the initial static Flash bit delay settings that are predefined by Libero SoC. The signal, “DELAY_LINE_MOVE” uses a rising edge to change the delay setting by ±1 increment each time it is pulsed according to the “DELAY_LINE_DIRECTION” signal value (a “1” increases up the delay setting by 1 increment and a “0” decreases down the delay setting by 1 increment). When the delay setting reaches the minimum value or the maximum value of the delay chain, the delay chain controller generates an out of range output Flag “DELAY_LINE_OUT_OF_RANGE” to indicate that it has reached the end of the delay chain. The delay setting stops at this minimum or maximum setting, even if the “DELAY_LINE_MOVE” signal is still pulsing.

The IOD block has a data eye monitor (DEM) used to optimize the clock and input data relationship. The DEM includes EYE_MONITOR_EARLY and EYE_MONITOR_LATE flags used to analyze the clock-to-data relationship. IOD designs can utilize these flags to determine the input data edge relationship to the clock edge. The design can then use the DELAY_LINE control inputs to dynamically adjust this relationship to optimize the clock and data relationships until an optimal setting is found.

Similarly, output delays are affected when the IOD tri-state enable “E” = 1 or the input delay “E” = 0. The DELAY_LINE_MOVE is applied to the output delay path.

The data edge monitoring (DEM) is accomplished as follows:

Figure 2. IOD Training Block Diagram