RX_DDR_G_C and RX_DDR_R_C—Centered Interfaces with Static Delays

The RX_DDR_G_C and RX_DDR_R_C interfaces have clock and data signals at the external input pins with the clock centered along the incoming data and uses a continuous clock as shown in the following figure. This interface strategy is similar to the aligned. The Libero SoC controlled input delay is set to cancel RX vs RX_CLK injection time to flip-flop. This is used to balance the clock and data delay—to the first flip-flop—to maintain the setup and hold requirements by compensating for the internal delays.

Figure 1. Centered Data and Clock Waveform

Using a global clock assignment receives RX data and RX_CLK clock through I/Os and passes RX_DATA and RX_CLK_R to the fabric. The input clock is passed directly to the GLOBAL CLKINT, sourced to the IOD logic, and forwarded to the fabric.

Global CLKINT resource drives the receive clock for fabric interface RX_CLK_R into the fabric.

Figure 2. RX_DDRX1 Centered Interface Using Global Clock

The RX_DDR centered interface using a lane clock assignment receives RX data and RX_CLK clock through I/Os, passes RX_DATA to the IOD, and RX_CLK_R to the lane controller. This uses a continuous clock. The lane controller manages the skew and passes the FAB_CLK to RCLKINT. The input clock is sent to both the IOD and to the fabric from RCLKINT.

RCLKINT resource drives the receive clock for fabric interface RX_CLK_R into the fabric.

Figure 3. RX_DDRX1 Centered Interface Using Regional Clock