RX_DDR_G_A/ RX_DDR_R_A—Aligned Interfaces with Static Delays

The RX_DDR_G_A and RX_DDR_R_A interfaces are used when the DDR data and clock signals are aligned at the external input pins as shown in the following figure. This interface uses a continuous clock. Internally, the aligned interface is required to adjust the clock to satisfy the capture flip-flop setup and hold times. The adjustments are done by input delay settings, which are automatically applied from the Libero SoC software. The interfaces shown in the following figure use a gearing ratio of 1 and the maximum X1 data rate. For more information about data rate, see respective PolarFire FPGA Datasheet or PolarFire SoC Advance Datasheet. There are two interface configurations based on clock source topology being either global or lane-based.

Figure 1. Aligned Data and Clock Waveform

In the RX_DDR aligned interface using a global clock assignment, it receives RX data and RX_CLK clock through I/Os and passes RX_DATA and RX_CLK_R to the fabric. The input clock is passed directly to the GLOBAL CLKINT that is sourced to the IOD logic. Libero SoC statically sets the input delay cells within the IOD to cancel RX vs RX_CLK injection time to flip-flop, plus an additional offset to internally center the data/clock relationship.

Global CLKINT resource drives the receive clock for fabric interface RX_CLK_R into the fabric.

Figure 2. RX_DDRX1 Aligned Interface Using Global Clock

The RX_DDR aligned interface using a lane clock assignment receives RX data and RX_CLK clock through I/Os and passes RX_DATA to the IOD. This is an aligned interface using a regional system clock distribution. This uses a continuous clock. RX_CLK is sent to the lane controller. The lane controller manages the skew and passes the FAB_CLK to a RCLKINT. The clock is sent to both the IOD and to the fabric from RCLKINT. Libero SoC statically sets the input delay cells within the IOD to cancel RX vs RX_CLK injection time to flip-flop, plus an offset to internally center the data/clock relationship.

The receive clock for fabric interface RX_CLK_R, is driven by RCLKINT resource into the fabric.

Figure 3. RX_DDRX1 Aligned Interface Using Regional Clock