RGMII to GMII Converter

Reduced gigabit media independent interface (RGMII) is a standard interface, which helps in reducing the number of signals required to connect a PHY to a MAC. RGMII to GMII converter provides the interface between a standard gigabit media independent interface (GMII) to RGMII conversion. The IP core is compatible with the RGMII specification v2.0 that is designed to support both the device family using the IOD blocks used with GPIO or HSIO buffers.

Figure 1. RGMII to GMII Block Diagram

The fifteen-signal GMII fabric interface adapts to six-signal RGMII interface by using both edges of the clock. All signals are synchronous with a 125 MHz clock signal. The RGMII data signals switch on the positive and negative edges of the clock. The two control signals are multiplexed—one arrives on the positive clock edge, the other on the negative edge. The PF_IOD_GENERIC_TX converts GMII signals (MAC side) to RGMII signals (PHY side), and the PF_IOD_GENERIC_RX converts the RGMII signals into GMII signals and passes the signals to the CoreRGMII IP block before transmission to the MAC. Externally, a 1000BASE-T Ethernet PHY is connected to RGMII through GPIO or HSIO.

See UG0687: PolarFire FPGA 1G Ethernet Solutions User Guide for more information.

The following table lists the GMII/RGMII ports and description.

Table 1. GMII Ports
Port I/O Description
GMII_TXCLK Input Clock from fabric (GTXCLK)
GMII_TXD [7:0] Input GMII transmit data
GMII_TX_EN Input Transmit enable
GMII_RXCLK Output Clock to fabric depending on RX clock configurator option, either fabric global or fabric regional via the iod_generic_tx block
GMII_TX_ER Input Transmit error
GMII_RXD[7:0] Output MII receive data
GMII_RX_DV Output Receive data valid
GMII_RX_ER Output Receive error
GMII_COL Output Collision, considered asynchronous
GMII_CRS Output Carrier sense, considered asynchronous
RGMII_TXD[3:0] Output Transmit data to PHY
RGMII_TX_CTL Output Transmit Control To PHY. The TX_CTL signal carries: 
– GMII_TX_EN on the rising edge 
– TX_EN or GMII_TX_ER on the falling edge
RGMII_RXD[3:0] Input Receive data from PHY
RGMII_RX_CTL Input Receive control from PHY. The RX_CTL signal carries: 
– gmii_rx_dv (data valid) on the rising edge 
– gmii_rx_dv xor gmii_rx_er on the falling edge
RGMII_RXC Input RGMII receive clock
RGMII_TXC Input RGMII transmit clock

The following figure shows the RGMII to GMII configurator.

Figure 2. RGMII to GMII Configurator

Both RX and TX IOD sub-modules are within the PF_RGMII_TO_GMII conversion module. Both blocks are pre-configured for the proper clock and data alignment and gearing ratios. You are not required to change the default setting for these modules but may need to be aware of the actual configurations for informational purposes. Designs using the PF_RGMII_TO_GMII conversion module must reference the pin selection rules discussed in Interface Selection Rules.