Interface Selection Rules

The following rules apply when assigning a pin to the RX_DDR_G_A aligned interface:

• Up to 12 single-ended data I/O and six differential data I/O.
• RX_CLK input must be placed in an I/O with the CLKIN_z_w function in the same bank as other I/Os.
• One IOD per data I/Os.
• One IOA per data and clock I/Os.
• RX IOA can be freely placed.

The following rules apply when assigning a pin to the RX_DDR_R_A aligned interface:

• Up to 11 single-ended data I/O and five differential data I/O.
• Uses one LANECTRL to connect to regional clock.
• Uses one regional clock.
• RX and RX_CLK I/Os must be placed in the same I/O lane.
• RX_CLK input must be placed in the P side I/O with the DQS function in the lane.
• RX and RX_CLK I/Os must be placed in the same bank (RX and RX_CLK I/O pins can be shared across banks 0 and 7).
• One IOD per data I/Os.
• One IOA per data and clock I/Os.