MIPI D-PHY Transmit Interface (High-speed Only) with Bidirectional Low-Power Mode

GPIO also supports a bidirectional MIPI D-PHY lane with external resistors, as shown in the following illustration. Microchip provides a macro that can be instantiated in the user design to implement the MIPI transmit interface (high-speed only) with bidirectional low-power mode, see Generic I/O Interfaces for more information.

Figure 1. High-Speed Transmit with Bidirectional
Note: See respective UG0726: PolarFire FPGA Board Design User Guide or PolarFire SoC FPGA Board Design Guidelines User Guide for resistor specifications.
Note: For information about implementation, see DG0807: PolarFire Imaging and Video Kit Demo Guide (MIPI CSI-2 Camera Sensor).