I/O Clock Networks

Each I/O contains a fabric clock connection, a high-speed I/O clock resource, and a lane controller clock resource for efficient clock distribution. All of these four clock networks can be used to interface with the IOD block.

There are some specific PolarFire FPGA IO clock differences along the North and South edges of the devices. The I/O span width of HS_IO_CLK trees on the North Edge is different across Banks 0, 1, and 7 in the MPF300/MPF500. There is no Bank 7 in MPF100/MPF200.

Although, Bank 2 is available in all PolarFire FPGA devices, the I/O span width of the HS_IO_CLK trees varies between device sizes. MPF100/200 device sub-divides Bank 2 into two sub-banks. This means the HS_IO_CLK tree is split between the available I/O within Bank 2. For MPF300/500, there is one continuous Bank 2 and also includes Bank 6. In these devices, the HS_IO_CLK is not split within any Bank.

For more information about global clock network, see PolarFire FPGA and PolarFire SoC FPGA Clocking Resources User Guide.