MIPI D-PHY Transmit Only (High-speed and Low-power)

The MIPI Low-power (LP) transmit signaling uses pins located in either GPIO or HSIO banks using 1.2 V VDDI I/O bank supply using LVCMOS12 outputs. High-speed MIPI transmit signals must be in GPIO bank using a 2.5 V VDDI I/O bank supply using MIPIE25 emulated differential output drivers. The MIPI TX standards are implemented by using the resistor divider network for LP and High-speed (HS) signals, as shown in the following figure. For required pin-out planning of the HS and LP Tx pins. See respective UG0726: PolarFire FPGA Board Design User Guide or PolarFire SoC FPGA Board Design Guidelines User Guide.

Figure 1. MIPI D-PHY Transmit Interface (High-speed and Low-power)
Note: Resistor value vary based on optimal performance. See respective UG0726: PolarFire FPGA Board Design User Guide or PolarFire SoC FPGA Board Design Guidelines User Guide for resistor specifications.

MIPI D_PHY transmits the TXD_DATA out on to the TXD/TX_CLK MIPI pins when the HS_DATA_SEL/HS_CLK_SEL port is asserted controlling the OE of the HS differential driver. The HS_DATA_SEL/HS_CLK_SEL are optionally configured using the Libero SoC IOD configurator.

When HS_DATA_SEL/HS_CLK_SEL is asserted, both single-ended LVCMOS12 8 mA drivers are driven low by the IOD to ensure proper level shifting occurs for high-speed operation.

In LP operation, HS_DATA_SEL/HS_CLK_SEL de-assertion sends the LP_DATA and LP_CLK out to the TXLP/TX_CLK_LP MIPI pins while the HS_TX pair is disabled in a High-Z state.

FPGA fabric synchronization registers are required when clocking LP_DATA with RX_CLK_R of the IOD to ensure clean capture of the data.

The D-PHY transmit must be interfaced to the MIPI receiver using the terminated interface shown in Figure 1.