Interface Ports

The following table lists the RX_DDRX_B_G_DYN/ RX_DDRX_B_R_DYN interface mode ports.

Table 1. RX_DDRX_L_DYN Ports
Port I/O Description
RXD/RXD_N Input Differential input DDR data
RX_CLK_P/RX_CLK_N Input Differential input clock
ARST_N Input Asynchronous reset to IOD and lane controller
Lx_BIT_SLIP Input Bit slip input (per lane) from fabric is initiated by a rising edge of the slip signal from the core fabric. Lx_BIT_SLIP is not available for DDRX3.5 gearing.
Lx_RXD_DATA[m:0] Output DDR output to FPGA fabric, value depends on digital ratio
RX_CLK_R/RX_CLK_G Output Receive clock to FPGA fabric using a global (G) or regional (R) clock.
CLK_TRAIN_DONE Output Indicates HS_IO_CLK and system clock training is complete. See HS_IO_CLK and System Clock Training.
CLK_TRAIN_ERROR Output Indicates HS_IO_CLK and system clock training did not complete. See HS_IO_CLK and System Clock Training.
(1) For more information, see Dynamic Delay Control.  

The RX_DDRX_B_G_DYN/ RX_DDRX_B_R_DYN interface has bit slip input from fabric, called Lx_BIT_SLIP. The slip input pin is used for word alignment. The slip function is used in 2, 4, and 5 Digital Modes—slip 1 bit at a time.

Parent topic: RX_DDRX_B_G_DYN/ RX_DDRX_B_R_DYN