Interface Selection Rules

The following conditions are applicable when assigning pins to the TX_DDR_G_A interface:

Note: At least, one CCC/PLL is required for clock phasing.

An optional feature enables the transmit parallel clock to be sent out synchronously with data. This feature is useful for applications such as CameraLink. The option is found in the Advance tab of the TX_DDR configurator GUI > Misc section > Enable user control of clock pattern. The generated TX_DDR component has a port PF_IOD_TX_CLK:TX_DATA_0 that is in the module with the TX_CLK_DATA ports.